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Merge branch 'phylink-and-sfp-support'
Russell King says: ==================== phylink and sfp support This patch series introduces generic support for SFP sockets found on various Marvell based platforms. The idea here is to provide common SFP socket support which can be re-used by network drivers as appropriate, rather than each network driver having to re-implement SFP socket support. SFP sockets typically use other system resources, eg, I2C buses to read identifying information, and GPIOs to monitor socket state and control the socket. Meanwhile, some network drivers drive multiple ethernet ports from one instantiation of the driver. It is not desirable to block the initialisation of a network driver (thus denying other ports from being operational) if the resources for the SFP socket are not yet available. This means that an element of independence between the SFP support code and the driver is required. More than that, SFP modules effectively bring hotplug PHYs to networking - SFP copper modules normally contain a standard PHY accessed over the I2C bus, and it is desirable to read their state so network drivers can be appropriately configured. To add to the complexity, SFP modules can be connected in at least two places: 1. Directly to the serdes output of a MAC with no intervening PHY. For example: mvneta ----> SFP socket 2. To a PHY, for example: mvpp2 ---> PHY ---> copper | `-----> SFP socket This code supports both setups, although it's not fully implemented with scenario (2). Moreover, the link presented by the SFP module can be one of the 10Gbase-R family (for SFP+ sockets), SGMII or 1000base-X (for SFP sockets) depending on the module, and network drivers need to reconfigure themselves accordingly for the link to come up. For example, if the MAC is configured for SGMII and a fibre module is plugged in, the link won't come up until the MAC is reconfigured for 1000base-X mode. The SFP code manages the SFP socket - detecting the module, reading the identifying information, and managing the control and status signals. Importantly, it disables the SFP module transmitter when the MAC is down, so that the laser is turned off (but that is not a guarantee.) phylink provides the mechanisms necessary to manage the link modes, based on the SFP module type, and supports hot-plugging of the PHY without needing the MAC driver to be brought up and down on transitions. phylink also supports the classical static PHY and fixed-link modes. I currently (but not included in this series) have code to convert mvneta to use phylink, and the out of tree mvpp2x driver. I have nothing for the mvpp2 driver at present as that driver is only recently becoming functional on 10G hardware, and is missing a lot of features that are necessary to make things work correctly. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
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‎drivers/net/phy/Kconfig

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@@ -106,6 +106,16 @@ config MDIO_HISI_FEMAC
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This module provides a driver for the MDIO busses found in the
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Hisilicon SoC that have an Fast Ethernet MAC.
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109+
config MDIO_I2C
110+
tristate
111+
depends on I2C
112+
help
113+
Support I2C based PHYs. This provides a MDIO bus bridged
114+
to I2C to allow PHYs connected in I2C mode to be accessed
115+
using the existing infrastructure.
116+
117+
This is library mode.
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109119
config MDIO_MOXART
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tristate "MOXA ART MDIO interface support"
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depends on ARCH_MOXART
@@ -159,6 +169,16 @@ menuconfig PHYLIB
159169
devices. This option provides infrastructure for
160170
managing PHY devices.
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config PHYLINK
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tristate
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depends on NETDEVICES
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select PHYLIB
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select SWPHY
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help
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PHYlink models the link between the PHY and MAC, allowing fixed
179+
configuration links, PHYs, and Serdes links with MAC level
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autonegotiation modes.
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162182
if PHYLIB
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config SWPHY
@@ -180,6 +200,11 @@ config LED_TRIGGER_PHY
180200

181201
comment "MII PHY device drivers"
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config SFP
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tristate "SFP cage support"
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depends on I2C && PHYLINK
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select MDIO_I2C
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183208
config AMD_PHY
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tristate "AMD PHYs"
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---help---

‎drivers/net/phy/Makefile

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@@ -18,6 +18,7 @@ endif
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libphy-$(CONFIG_SWPHY) += swphy.o
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libphy-$(CONFIG_LED_TRIGGER_PHY) += phy_led_triggers.o
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obj-$(CONFIG_PHYLINK) += phylink.o
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obj-$(CONFIG_PHYLIB) += libphy.o
2223

2324
obj-$(CONFIG_MDIO_BCM_IPROC) += mdio-bcm-iproc.o
@@ -30,12 +31,17 @@ obj-$(CONFIG_MDIO_BUS_MUX_MMIOREG) += mdio-mux-mmioreg.o
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obj-$(CONFIG_MDIO_CAVIUM) += mdio-cavium.o
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obj-$(CONFIG_MDIO_GPIO) += mdio-gpio.o
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obj-$(CONFIG_MDIO_HISI_FEMAC) += mdio-hisi-femac.o
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obj-$(CONFIG_MDIO_I2C) += mdio-i2c.o
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obj-$(CONFIG_MDIO_MOXART) += mdio-moxart.o
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obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o
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obj-$(CONFIG_MDIO_SUN4I) += mdio-sun4i.o
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obj-$(CONFIG_MDIO_THUNDER) += mdio-thunder.o
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obj-$(CONFIG_MDIO_XGENE) += mdio-xgene.o
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41+
obj-$(CONFIG_SFP) += sfp.o
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sfp-obj-$(CONFIG_SFP) += sfp-bus.o
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obj-y += $(sfp-obj-y) $(sfp-obj-m)
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obj-$(CONFIG_AMD_PHY) += amd.o
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obj-$(CONFIG_AQUANTIA_PHY) += aquantia.o
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obj-$(CONFIG_AT803X_PHY) += at803x.o

‎drivers/net/phy/mdio-i2c.c

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@@ -0,0 +1,109 @@
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/*
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* MDIO I2C bridge
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*
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* Copyright (C) 2015-2016 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Network PHYs can appear on I2C buses when they are part of SFP module.
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* This driver exposes these PHYs to the networking PHY code, allowing
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* our PHY drivers access to these PHYs, and so allowing configuration
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* of their settings.
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*/
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#include <linux/i2c.h>
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#include <linux/phy.h>
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#include "mdio-i2c.h"
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/*
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* I2C bus addresses 0x50 and 0x51 are normally an EEPROM, which is
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* specified to be present in SFP modules. These correspond with PHY
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* addresses 16 and 17. Disallow access to these "phy" addresses.
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*/
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static bool i2c_mii_valid_phy_id(int phy_id)
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{
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return phy_id != 0x10 && phy_id != 0x11;
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}
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static unsigned int i2c_mii_phy_addr(int phy_id)
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{
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return phy_id + 0x40;
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}
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static int i2c_mii_read(struct mii_bus *bus, int phy_id, int reg)
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{
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struct i2c_adapter *i2c = bus->priv;
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struct i2c_msg msgs[2];
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u8 data[2], dev_addr = reg;
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int bus_addr, ret;
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if (!i2c_mii_valid_phy_id(phy_id))
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return 0xffff;
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bus_addr = i2c_mii_phy_addr(phy_id);
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msgs[0].addr = bus_addr;
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msgs[0].flags = 0;
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msgs[0].len = 1;
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msgs[0].buf = &dev_addr;
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msgs[1].addr = bus_addr;
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msgs[1].flags = I2C_M_RD;
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msgs[1].len = sizeof(data);
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msgs[1].buf = data;
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55+
ret = i2c_transfer(i2c, msgs, ARRAY_SIZE(msgs));
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if (ret != ARRAY_SIZE(msgs))
57+
return 0xffff;
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59+
return data[0] << 8 | data[1];
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}
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static int i2c_mii_write(struct mii_bus *bus, int phy_id, int reg, u16 val)
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{
64+
struct i2c_adapter *i2c = bus->priv;
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struct i2c_msg msg;
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int ret;
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u8 data[3];
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if (!i2c_mii_valid_phy_id(phy_id))
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return 0;
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data[0] = reg;
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data[1] = val >> 8;
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data[2] = val;
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msg.addr = i2c_mii_phy_addr(phy_id);
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msg.flags = 0;
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msg.len = 3;
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msg.buf = data;
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ret = i2c_transfer(i2c, &msg, 1);
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return ret < 0 ? ret : 0;
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}
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struct mii_bus *mdio_i2c_alloc(struct device *parent, struct i2c_adapter *i2c)
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{
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struct mii_bus *mii;
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if (!i2c_check_functionality(i2c, I2C_FUNC_I2C))
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return ERR_PTR(-EINVAL);
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mii = mdiobus_alloc();
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if (!mii)
95+
return ERR_PTR(-ENOMEM);
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snprintf(mii->id, MII_BUS_ID_SIZE, "i2c:%s", dev_name(parent));
98+
mii->parent = parent;
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mii->read = i2c_mii_read;
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mii->write = i2c_mii_write;
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mii->priv = i2c;
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return mii;
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}
105+
EXPORT_SYMBOL_GPL(mdio_i2c_alloc);
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MODULE_AUTHOR("Russell King");
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MODULE_DESCRIPTION("MDIO I2C bridge library");
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MODULE_LICENSE("GPL v2");

‎drivers/net/phy/mdio-i2c.h

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@@ -0,0 +1,19 @@
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/*
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* MDIO I2C bridge
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*
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* Copyright (C) 2015 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
7+
* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef MDIO_I2C_H
11+
#define MDIO_I2C_H
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13+
struct device;
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struct i2c_adapter;
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struct mii_bus;
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struct mii_bus *mdio_i2c_alloc(struct device *parent, struct i2c_adapter *i2c);
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19+
#endif

‎drivers/net/phy/phy-core.c

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@@ -9,6 +9,186 @@
99
#include <linux/export.h>
1010
#include <linux/phy.h>
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const char *phy_speed_to_str(int speed)
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{
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switch (speed) {
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case SPEED_10:
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return "10Mbps";
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case SPEED_100:
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return "100Mbps";
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case SPEED_1000:
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return "1Gbps";
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case SPEED_2500:
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return "2.5Gbps";
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case SPEED_5000:
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return "5Gbps";
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case SPEED_10000:
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return "10Gbps";
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case SPEED_14000:
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return "14Gbps";
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case SPEED_20000:
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return "20Gbps";
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case SPEED_25000:
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return "25Gbps";
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case SPEED_40000:
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return "40Gbps";
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case SPEED_50000:
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return "50Gbps";
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case SPEED_56000:
38+
return "56Gbps";
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case SPEED_100000:
40+
return "100Gbps";
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case SPEED_UNKNOWN:
42+
return "Unknown";
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default:
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return "Unsupported (update phy-core.c)";
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}
46+
}
47+
EXPORT_SYMBOL_GPL(phy_speed_to_str);
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49+
const char *phy_duplex_to_str(unsigned int duplex)
50+
{
51+
if (duplex == DUPLEX_HALF)
52+
return "Half";
53+
if (duplex == DUPLEX_FULL)
54+
return "Full";
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if (duplex == DUPLEX_UNKNOWN)
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return "Unknown";
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return "Unsupported (update phy-core.c)";
58+
}
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EXPORT_SYMBOL_GPL(phy_duplex_to_str);
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/* A mapping of all SUPPORTED settings to speed/duplex. This table
62+
* must be grouped by speed and sorted in descending match priority
63+
* - iow, descending speed. */
64+
static const struct phy_setting settings[] = {
65+
{
66+
.speed = SPEED_10000,
67+
.duplex = DUPLEX_FULL,
68+
.bit = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
69+
},
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{
71+
.speed = SPEED_10000,
72+
.duplex = DUPLEX_FULL,
73+
.bit = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
74+
},
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{
76+
.speed = SPEED_10000,
77+
.duplex = DUPLEX_FULL,
78+
.bit = ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
79+
},
80+
{
81+
.speed = SPEED_2500,
82+
.duplex = DUPLEX_FULL,
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.bit = ETHTOOL_LINK_MODE_2500baseX_Full_BIT,
84+
},
85+
{
86+
.speed = SPEED_1000,
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.duplex = DUPLEX_FULL,
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.bit = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
89+
},
90+
{
91+
.speed = SPEED_1000,
92+
.duplex = DUPLEX_FULL,
93+
.bit = ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
94+
},
95+
{
96+
.speed = SPEED_1000,
97+
.duplex = DUPLEX_FULL,
98+
.bit = ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
99+
},
100+
{
101+
.speed = SPEED_1000,
102+
.duplex = DUPLEX_HALF,
103+
.bit = ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
104+
},
105+
{
106+
.speed = SPEED_100,
107+
.duplex = DUPLEX_FULL,
108+
.bit = ETHTOOL_LINK_MODE_100baseT_Full_BIT,
109+
},
110+
{
111+
.speed = SPEED_100,
112+
.duplex = DUPLEX_HALF,
113+
.bit = ETHTOOL_LINK_MODE_100baseT_Half_BIT,
114+
},
115+
{
116+
.speed = SPEED_10,
117+
.duplex = DUPLEX_FULL,
118+
.bit = ETHTOOL_LINK_MODE_10baseT_Full_BIT,
119+
},
120+
{
121+
.speed = SPEED_10,
122+
.duplex = DUPLEX_HALF,
123+
.bit = ETHTOOL_LINK_MODE_10baseT_Half_BIT,
124+
},
125+
};
126+
127+
/**
128+
* phy_lookup_setting - lookup a PHY setting
129+
* @speed: speed to match
130+
* @duplex: duplex to match
131+
* @mask: allowed link modes
132+
* @maxbit: bit size of link modes
133+
* @exact: an exact match is required
134+
*
135+
* Search the settings array for a setting that matches the speed and
136+
* duplex, and which is supported.
137+
*
138+
* If @exact is unset, either an exact match or %NULL for no match will
139+
* be returned.
140+
*
141+
* If @exact is set, an exact match, the fastest supported setting at
142+
* or below the specified speed, the slowest supported setting, or if
143+
* they all fail, %NULL will be returned.
144+
*/
145+
const struct phy_setting *
146+
phy_lookup_setting(int speed, int duplex, const unsigned long *mask,
147+
size_t maxbit, bool exact)
148+
{
149+
const struct phy_setting *p, *match = NULL, *last = NULL;
150+
int i;
151+
152+
for (i = 0, p = settings; i < ARRAY_SIZE(settings); i++, p++) {
153+
if (p->bit < maxbit && test_bit(p->bit, mask)) {
154+
last = p;
155+
if (p->speed == speed && p->duplex == duplex) {
156+
/* Exact match for speed and duplex */
157+
match = p;
158+
break;
159+
} else if (!exact) {
160+
if (!match && p->speed <= speed)
161+
/* Candidate */
162+
match = p;
163+
164+
if (p->speed < speed)
165+
break;
166+
}
167+
}
168+
}
169+
170+
if (!match && !exact)
171+
match = last;
172+
173+
return match;
174+
}
175+
EXPORT_SYMBOL_GPL(phy_lookup_setting);
176+
177+
size_t phy_speeds(unsigned int *speeds, size_t size,
178+
unsigned long *mask, size_t maxbit)
179+
{
180+
size_t count;
181+
int i;
182+
183+
for (i = 0, count = 0; i < ARRAY_SIZE(settings) && count < size; i++)
184+
if (settings[i].bit < maxbit &&
185+
test_bit(settings[i].bit, mask) &&
186+
(count == 0 || speeds[count - 1] != settings[i].speed))
187+
speeds[count++] = settings[i].speed;
188+
189+
return count;
190+
}
191+
12192
static void mmd_phy_indirect(struct mii_bus *bus, int phy_addr, int devad,
13193
u16 regnum)
14194
{

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