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oulijunjgunthorpe
oulijun
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jgunthorpe
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RDMA/hns: Update some fields of qp context
The hip08 hardware has two version. the version id are 0x20 and 0x21 according to the pci revision. It needs to adjust some fields for extending new features. The specific updates include: 1. Add some fields for supporting new features by enabling some reserved fields in 0x20 version. 2. remove some fields which the user is not visiable in order to support the extend features. 3. Init some fields with zero. These updates is compatible with 0x20 version. Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
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-66
lines changed

2 files changed

+45
-66
lines changed

‎drivers/infiniband/hw/hns/hns_roce_hw_v2.c

Lines changed: 27 additions & 42 deletions
Original file line numberDiff line numberDiff line change
@@ -2670,21 +2670,16 @@ static void modify_qp_reset_to_init(struct ib_qp *ibqp,
26702670
roce_set_bit(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_RQ_TX_ERR_S, 0);
26712671
roce_set_bit(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_RQ_RX_ERR_S, 0);
26722672

2673-
roce_set_field(qpc_mask->byte_60_qpst_mapid, V2_QPC_BYTE_60_MAPID_M,
2674-
V2_QPC_BYTE_60_MAPID_S, 0);
2673+
roce_set_field(qpc_mask->byte_60_qpst_tempid, V2_QPC_BYTE_60_TEMPID_M,
2674+
V2_QPC_BYTE_60_TEMPID_S, 0);
26752675

2676-
roce_set_bit(qpc_mask->byte_60_qpst_mapid,
2677-
V2_QPC_BYTE_60_INNER_MAP_IND_S, 0);
2678-
roce_set_bit(qpc_mask->byte_60_qpst_mapid, V2_QPC_BYTE_60_SQ_MAP_IND_S,
2679-
0);
2680-
roce_set_bit(qpc_mask->byte_60_qpst_mapid, V2_QPC_BYTE_60_RQ_MAP_IND_S,
2681-
0);
2682-
roce_set_bit(qpc_mask->byte_60_qpst_mapid, V2_QPC_BYTE_60_EXT_MAP_IND_S,
2683-
0);
2684-
roce_set_bit(qpc_mask->byte_60_qpst_mapid, V2_QPC_BYTE_60_SQ_RLS_IND_S,
2685-
0);
2686-
roce_set_bit(qpc_mask->byte_60_qpst_mapid, V2_QPC_BYTE_60_SQ_EXT_IND_S,
2687-
0);
2676+
roce_set_field(qpc_mask->byte_60_qpst_tempid,
2677+
V2_QPC_BYTE_60_SCC_TOKEN_M, V2_QPC_BYTE_60_SCC_TOKEN_S,
2678+
0);
2679+
roce_set_bit(qpc_mask->byte_60_qpst_tempid,
2680+
V2_QPC_BYTE_60_SQ_DB_DOING_S, 0);
2681+
roce_set_bit(qpc_mask->byte_60_qpst_tempid,
2682+
V2_QPC_BYTE_60_RQ_DB_DOING_S, 0);
26882683
roce_set_bit(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_CNP_TX_FLAG_S, 0);
26892684
roce_set_bit(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_CE_FLAG_S, 0);
26902685

@@ -2766,7 +2761,8 @@ static void modify_qp_reset_to_init(struct ib_qp *ibqp,
27662761
roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_TAIL_MAX_M,
27672762
V2_QPC_BYTE_132_TRRL_TAIL_MAX_S, 0);
27682763

2769-
roce_set_bit(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_RSVD_RAQ_MAP_S, 0);
2764+
roce_set_bit(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_RQ_RTY_WAIT_DO_S,
2765+
0);
27702766
roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_RAQ_TRRL_HEAD_M,
27712767
V2_QPC_BYTE_140_RAQ_TRRL_HEAD_S, 0);
27722768
roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_RAQ_TRRL_TAIL_M,
@@ -2775,8 +2771,6 @@ static void modify_qp_reset_to_init(struct ib_qp *ibqp,
27752771
roce_set_field(qpc_mask->byte_144_raq,
27762772
V2_QPC_BYTE_144_RAQ_RTY_INI_PSN_M,
27772773
V2_QPC_BYTE_144_RAQ_RTY_INI_PSN_S, 0);
2778-
roce_set_bit(qpc_mask->byte_144_raq, V2_QPC_BYTE_144_RAQ_RTY_INI_IND_S,
2779-
0);
27802774
roce_set_field(qpc_mask->byte_144_raq, V2_QPC_BYTE_144_RAQ_CREDIT_M,
27812775
V2_QPC_BYTE_144_RAQ_CREDIT_S, 0);
27822776
roce_set_bit(qpc_mask->byte_144_raq, V2_QPC_BYTE_144_RESP_RTY_FLG_S, 0);
@@ -2802,14 +2796,12 @@ static void modify_qp_reset_to_init(struct ib_qp *ibqp,
28022796
V2_QPC_BYTE_160_SQ_CONSUMER_IDX_M,
28032797
V2_QPC_BYTE_160_SQ_CONSUMER_IDX_S, 0);
28042798

2805-
roce_set_field(context->byte_168_irrl_idx,
2806-
V2_QPC_BYTE_168_SQ_SHIFT_BAK_M,
2807-
V2_QPC_BYTE_168_SQ_SHIFT_BAK_S,
2808-
ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2809-
roce_set_field(qpc_mask->byte_168_irrl_idx,
2810-
V2_QPC_BYTE_168_SQ_SHIFT_BAK_M,
2811-
V2_QPC_BYTE_168_SQ_SHIFT_BAK_S, 0);
2812-
2799+
roce_set_bit(qpc_mask->byte_168_irrl_idx,
2800+
V2_QPC_BYTE_168_POLL_DB_WAIT_DO_S, 0);
2801+
roce_set_bit(qpc_mask->byte_168_irrl_idx,
2802+
V2_QPC_BYTE_168_SCC_TOKEN_FORBID_SQ_DEQ_S, 0);
2803+
roce_set_bit(qpc_mask->byte_168_irrl_idx,
2804+
V2_QPC_BYTE_168_WAIT_ACK_TIMEOUT_S, 0);
28132805
roce_set_bit(qpc_mask->byte_168_irrl_idx,
28142806
V2_QPC_BYTE_168_MSG_RTY_LP_FLG_S, 0);
28152807
roce_set_bit(qpc_mask->byte_168_irrl_idx,
@@ -2871,6 +2863,13 @@ static void modify_qp_reset_to_init(struct ib_qp *ibqp,
28712863
V2_QPC_BYTE_232_IRRL_SGE_IDX_M,
28722864
V2_QPC_BYTE_232_IRRL_SGE_IDX_S, 0);
28732865

2866+
roce_set_bit(qpc_mask->byte_232_irrl_sge, V2_QPC_BYTE_232_SO_LP_VLD_S,
2867+
0);
2868+
roce_set_bit(qpc_mask->byte_232_irrl_sge,
2869+
V2_QPC_BYTE_232_FENCE_LP_VLD_S, 0);
2870+
roce_set_bit(qpc_mask->byte_232_irrl_sge, V2_QPC_BYTE_232_IRRL_LP_VLD_S,
2871+
0);
2872+
28742873
qpc_mask->irrl_cur_sge_offset = 0;
28752874

28762875
roce_set_field(qpc_mask->byte_240_irrl_tail,
@@ -3036,13 +3035,6 @@ static void modify_qp_init_to_init(struct ib_qp *ibqp,
30363035
roce_set_field(qpc_mask->byte_56_dqpn_err,
30373036
V2_QPC_BYTE_56_DQPN_M, V2_QPC_BYTE_56_DQPN_S, 0);
30383037
}
3039-
roce_set_field(context->byte_168_irrl_idx,
3040-
V2_QPC_BYTE_168_SQ_SHIFT_BAK_M,
3041-
V2_QPC_BYTE_168_SQ_SHIFT_BAK_S,
3042-
ilog2((unsigned int)hr_qp->sq.wqe_cnt));
3043-
roce_set_field(qpc_mask->byte_168_irrl_idx,
3044-
V2_QPC_BYTE_168_SQ_SHIFT_BAK_M,
3045-
V2_QPC_BYTE_168_SQ_SHIFT_BAK_S, 0);
30463038
}
30473039

30483040
static int modify_qp_init_to_rtr(struct ib_qp *ibqp,
@@ -3352,13 +3344,6 @@ static int modify_qp_rtr_to_rts(struct ib_qp *ibqp,
33523344
* we should set all bits of the relevant fields in context mask to
33533345
* 0 at the same time, else set them to 0x1.
33543346
*/
3355-
roce_set_field(context->byte_60_qpst_mapid,
3356-
V2_QPC_BYTE_60_RTY_NUM_INI_BAK_M,
3357-
V2_QPC_BYTE_60_RTY_NUM_INI_BAK_S, attr->retry_cnt);
3358-
roce_set_field(qpc_mask->byte_60_qpst_mapid,
3359-
V2_QPC_BYTE_60_RTY_NUM_INI_BAK_M,
3360-
V2_QPC_BYTE_60_RTY_NUM_INI_BAK_S, 0);
3361-
33623347
context->sq_cur_blk_addr = (u32)(mtts[0] >> PAGE_ADDR_SHIFT);
33633348
roce_set_field(context->byte_168_irrl_idx,
33643349
V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_M,
@@ -3694,9 +3679,9 @@ static int hns_roce_v2_modify_qp(struct ib_qp *ibqp,
36943679
set_access_flags(hr_qp, context, qpc_mask, attr, attr_mask);
36953680

36963681
/* Every status migrate must change state */
3697-
roce_set_field(context->byte_60_qpst_mapid, V2_QPC_BYTE_60_QP_ST_M,
3682+
roce_set_field(context->byte_60_qpst_tempid, V2_QPC_BYTE_60_QP_ST_M,
36983683
V2_QPC_BYTE_60_QP_ST_S, new_state);
3699-
roce_set_field(qpc_mask->byte_60_qpst_mapid, V2_QPC_BYTE_60_QP_ST_M,
3684+
roce_set_field(qpc_mask->byte_60_qpst_tempid, V2_QPC_BYTE_60_QP_ST_M,
37003685
V2_QPC_BYTE_60_QP_ST_S, 0);
37013686

37023687
/* SW pass context to HW */
@@ -3816,7 +3801,7 @@ static int hns_roce_v2_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
38163801
goto out;
38173802
}
38183803

3819-
state = roce_get_field(context->byte_60_qpst_mapid,
3804+
state = roce_get_field(context->byte_60_qpst_tempid,
38203805
V2_QPC_BYTE_60_QP_ST_M, V2_QPC_BYTE_60_QP_ST_S);
38213806
tmp_qp_state = to_ib_qp_st((enum hns_roce_v2_qp_state)state);
38223807
if (tmp_qp_state == -1) {

‎drivers/infiniband/hw/hns/hns_roce_hw_v2.h

Lines changed: 18 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -354,7 +354,7 @@ struct hns_roce_v2_qp_context {
354354
__le32 dmac;
355355
__le32 byte_52_udpspn_dmac;
356356
__le32 byte_56_dqpn_err;
357-
__le32 byte_60_qpst_mapid;
357+
__le32 byte_60_qpst_tempid;
358358
__le32 qkey_xrcd;
359359
__le32 byte_68_rq_db;
360360
__le32 rq_db_record_addr;
@@ -496,26 +496,15 @@ struct hns_roce_v2_qp_context {
496496
#define V2_QPC_BYTE_56_LP_PKTN_INI_S 28
497497
#define V2_QPC_BYTE_56_LP_PKTN_INI_M GENMASK(31, 28)
498498

499-
#define V2_QPC_BYTE_60_MAPID_S 0
500-
#define V2_QPC_BYTE_60_MAPID_M GENMASK(12, 0)
499+
#define V2_QPC_BYTE_60_TEMPID_S 0
500+
#define V2_QPC_BYTE_60_TEMPID_M GENMASK(7, 0)
501501

502-
#define V2_QPC_BYTE_60_INNER_MAP_IND_S 13
502+
#define V2_QPC_BYTE_60_SCC_TOKEN_S 8
503+
#define V2_QPC_BYTE_60_SCC_TOKEN_M GENMASK(26, 8)
503504

504-
#define V2_QPC_BYTE_60_SQ_MAP_IND_S 14
505+
#define V2_QPC_BYTE_60_SQ_DB_DOING_S 27
505506

506-
#define V2_QPC_BYTE_60_RQ_MAP_IND_S 15
507-
508-
#define V2_QPC_BYTE_60_TEMPID_S 16
509-
#define V2_QPC_BYTE_60_TEMPID_M GENMASK(22, 16)
510-
511-
#define V2_QPC_BYTE_60_EXT_MAP_IND_S 23
512-
513-
#define V2_QPC_BYTE_60_RTY_NUM_INI_BAK_S 24
514-
#define V2_QPC_BYTE_60_RTY_NUM_INI_BAK_M GENMASK(26, 24)
515-
516-
#define V2_QPC_BYTE_60_SQ_RLS_IND_S 27
517-
518-
#define V2_QPC_BYTE_60_SQ_EXT_IND_S 28
507+
#define V2_QPC_BYTE_60_RQ_DB_DOING_S 28
519508

520509
#define V2_QPC_BYTE_60_QP_ST_S 29
521510
#define V2_QPC_BYTE_60_QP_ST_M GENMASK(31, 29)
@@ -592,7 +581,7 @@ struct hns_roce_v2_qp_context {
592581
#define V2_QPC_BYTE_140_RR_MAX_S 12
593582
#define V2_QPC_BYTE_140_RR_MAX_M GENMASK(14, 12)
594583

595-
#define V2_QPC_BYTE_140_RSVD_RAQ_MAP_S 15
584+
#define V2_QPC_BYTE_140_RQ_RTY_WAIT_DO_S 15
596585

597586
#define V2_QPC_BYTE_140_RAQ_TRRL_HEAD_S 16
598587
#define V2_QPC_BYTE_140_RAQ_TRRL_HEAD_M GENMASK(23, 16)
@@ -603,8 +592,6 @@ struct hns_roce_v2_qp_context {
603592
#define V2_QPC_BYTE_144_RAQ_RTY_INI_PSN_S 0
604593
#define V2_QPC_BYTE_144_RAQ_RTY_INI_PSN_M GENMASK(23, 0)
605594

606-
#define V2_QPC_BYTE_144_RAQ_RTY_INI_IND_S 24
607-
608595
#define V2_QPC_BYTE_144_RAQ_CREDIT_S 25
609596
#define V2_QPC_BYTE_144_RAQ_CREDIT_M GENMASK(29, 25)
610597

@@ -641,9 +628,9 @@ struct hns_roce_v2_qp_context {
641628
#define V2_QPC_BYTE_168_LP_SGEN_INI_S 22
642629
#define V2_QPC_BYTE_168_LP_SGEN_INI_M GENMASK(23, 22)
643630

644-
#define V2_QPC_BYTE_168_SQ_SHIFT_BAK_S 24
645-
#define V2_QPC_BYTE_168_SQ_SHIFT_BAK_M GENMASK(27, 24)
646-
631+
#define V2_QPC_BYTE_168_POLL_DB_WAIT_DO_S 25
632+
#define V2_QPC_BYTE_168_SCC_TOKEN_FORBID_SQ_DEQ_S 26
633+
#define V2_QPC_BYTE_168_WAIT_ACK_TIMEOUT_S 27
647634
#define V2_QPC_BYTE_168_IRRL_IDX_LSB_S 28
648635
#define V2_QPC_BYTE_168_IRRL_IDX_LSB_M GENMASK(31, 28)
649636

@@ -729,6 +716,10 @@ struct hns_roce_v2_qp_context {
729716
#define V2_QPC_BYTE_232_IRRL_SGE_IDX_S 20
730717
#define V2_QPC_BYTE_232_IRRL_SGE_IDX_M GENMASK(28, 20)
731718

719+
#define V2_QPC_BYTE_232_SO_LP_VLD_S 29
720+
#define V2_QPC_BYTE_232_FENCE_LP_VLD_S 30
721+
#define V2_QPC_BYTE_232_IRRL_LP_VLD_S 31
722+
732723
#define V2_QPC_BYTE_240_IRRL_TAIL_REAL_S 0
733724
#define V2_QPC_BYTE_240_IRRL_TAIL_REAL_M GENMASK(7, 0)
734725

@@ -747,6 +738,9 @@ struct hns_roce_v2_qp_context {
747738
#define V2_QPC_BYTE_244_RNR_CNT_S 27
748739
#define V2_QPC_BYTE_244_RNR_CNT_M GENMASK(29, 27)
749740

741+
#define V2_QPC_BYTE_244_LCL_OP_FLG_S 30
742+
#define V2_QPC_BYTE_244_IRRL_RD_FLG_S 31
743+
750744
#define V2_QPC_BYTE_248_IRRL_PSN_S 0
751745
#define V2_QPC_BYTE_248_IRRL_PSN_M GENMASK(23, 0)
752746

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