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moepinetmartinkpetersen
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scsi: mpt3sas: fix memory ordering on 64bit writes
With commit 09c2f95 ("scsi: mpt3sas: Swap I/O memory read value back to cpu endianness"), 64bit writes in _base_writeq() were rewritten to use __raw_writeq() instad of writeq(). This introduced a bug apparent on powerpc64 systems such as the Raptor Talos II that causes the HBA to drop from the PCIe bus under heavy load and being reinitialized after a couple of seconds. It can easily be triggered on affacted systems by using something like fio --name=random-write --iodepth=4 --rw=randwrite --bs=4k --direct=0 \ --size=128M --numjobs=64 --end_fsync=1 fio --name=random-write --iodepth=4 --rw=randwrite --bs=64k --direct=0 \ --size=128M --numjobs=64 --end_fsync=1 a couple of times. In my case I tested it on both a ZFS raidz2 and a btrfs raid6 using LSI 9300-8i and 9400-8i controllers. The fix consists in resembling the write ordering of writeq() by adding a mandatory write memory barrier before device access and a compiler barrier afterwards. The additional MMIO barrier is superfluous. Signed-off-by: Stephan Günther <moepi@moepi.net> Reported-by: Matt Corallo <linux@bluematt.me> Acked-by: Sreekanth Reddy <Sreekanth.Reddy@broadcom.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
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drivers/scsi/mpt3sas/mpt3sas_base.c

Lines changed: 2 additions & 1 deletion
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@@ -3345,8 +3345,9 @@ _base_mpi_ep_writeq(__u64 b, volatile void __iomem *addr,
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static inline void
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_base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock)
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{
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wmb();
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__raw_writeq(b, addr);
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mmiowb();
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barrier();
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}
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#else
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static inline void

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