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powerpc/xive: Native exploitation of the XIVE interrupt controller
The XIVE interrupt controller is the new interrupt controller found in POWER9. It supports advanced virtualization capabilities among other things. Currently we use a set of firmware calls that simulate the old "XICS" interrupt controller but this is fairly inefficient. This adds the framework for using XIVE along with a native backend which OPAL for configuration. Later, a backend allowing the use in a KVM or PowerVM guest will also be provided. This disables some fast path for interrupts in KVM when XIVE is enabled as these rely on the firmware emulation code which is no longer available when the XIVE is used natively by Linux. A latter patch will make KVM also directly exploit the XIVE, thus recovering the lost performance (and more). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [mpe: Fixup pr_xxx("XIVE:"...), don't split pr_xxx() strings, tweak Kconfig so XIVE_NATIVE selects XIVE and depends on POWERNV, fix build errors when SMP=n, fold in fixes from Ben: Don't call cpu_online() on an invalid CPU number Fix irq target selection returning out of bounds cpu# Extra sanity checks on cpu numbers ] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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‎arch/powerpc/include/asm/xive-regs.h

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/*
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* Copyright 2016,2017 IBM Corporation.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#ifndef _ASM_POWERPC_XIVE_REGS_H
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#define _ASM_POWERPC_XIVE_REGS_H
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/*
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* Thread Management (aka "TM") registers
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*/
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/* TM register offsets */
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#define TM_QW0_USER 0x000 /* All rings */
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#define TM_QW1_OS 0x010 /* Ring 0..2 */
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#define TM_QW2_HV_POOL 0x020 /* Ring 0..1 */
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#define TM_QW3_HV_PHYS 0x030 /* Ring 0..1 */
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/* Byte offsets inside a QW QW0 QW1 QW2 QW3 */
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#define TM_NSR 0x0 /* + + - + */
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#define TM_CPPR 0x1 /* - + - + */
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#define TM_IPB 0x2 /* - + + + */
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#define TM_LSMFB 0x3 /* - + + + */
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#define TM_ACK_CNT 0x4 /* - + - - */
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#define TM_INC 0x5 /* - + - + */
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#define TM_AGE 0x6 /* - + - + */
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#define TM_PIPR 0x7 /* - + - + */
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#define TM_WORD0 0x0
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#define TM_WORD1 0x4
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/*
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* QW word 2 contains the valid bit at the top and other fields
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* depending on the QW.
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*/
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#define TM_WORD2 0x8
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#define TM_QW0W2_VU PPC_BIT32(0)
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#define TM_QW0W2_LOGIC_SERV PPC_BITMASK32(1,31) // XX 2,31 ?
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#define TM_QW1W2_VO PPC_BIT32(0)
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#define TM_QW1W2_OS_CAM PPC_BITMASK32(8,31)
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#define TM_QW2W2_VP PPC_BIT32(0)
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#define TM_QW2W2_POOL_CAM PPC_BITMASK32(8,31)
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#define TM_QW3W2_VT PPC_BIT32(0)
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#define TM_QW3W2_LP PPC_BIT32(6)
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#define TM_QW3W2_LE PPC_BIT32(7)
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#define TM_QW3W2_T PPC_BIT32(31)
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/*
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* In addition to normal loads to "peek" and writes (only when invalid)
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* using 4 and 8 bytes accesses, the above registers support these
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* "special" byte operations:
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*
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* - Byte load from QW0[NSR] - User level NSR (EBB)
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* - Byte store to QW0[NSR] - User level NSR (EBB)
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* - Byte load/store to QW1[CPPR] and QW3[CPPR] - CPPR access
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* - Byte load from QW3[TM_WORD2] - Read VT||00000||LP||LE on thrd 0
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* otherwise VT||0000000
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* - Byte store to QW3[TM_WORD2] - Set VT bit (and LP/LE if present)
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*
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* Then we have all these "special" CI ops at these offset that trigger
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* all sorts of side effects:
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*/
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#define TM_SPC_ACK_EBB 0x800 /* Load8 ack EBB to reg*/
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#define TM_SPC_ACK_OS_REG 0x810 /* Load16 ack OS irq to reg */
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#define TM_SPC_PUSH_USR_CTX 0x808 /* Store32 Push/Validate user context */
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#define TM_SPC_PULL_USR_CTX 0x808 /* Load32 Pull/Invalidate user context */
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#define TM_SPC_SET_OS_PENDING 0x812 /* Store8 Set OS irq pending bit */
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#define TM_SPC_PULL_OS_CTX 0x818 /* Load32/Load64 Pull/Invalidate OS context to reg */
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#define TM_SPC_PULL_POOL_CTX 0x828 /* Load32/Load64 Pull/Invalidate Pool context to reg*/
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#define TM_SPC_ACK_HV_REG 0x830 /* Load16 ack HV irq to reg */
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#define TM_SPC_PULL_USR_CTX_OL 0xc08 /* Store8 Pull/Inval usr ctx to odd line */
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#define TM_SPC_ACK_OS_EL 0xc10 /* Store8 ack OS irq to even line */
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#define TM_SPC_ACK_HV_POOL_EL 0xc20 /* Store8 ack HV evt pool to even line */
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#define TM_SPC_ACK_HV_EL 0xc30 /* Store8 ack HV irq to even line */
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/* XXX more... */
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/* NSR fields for the various QW ack types */
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#define TM_QW0_NSR_EB PPC_BIT8(0)
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#define TM_QW1_NSR_EO PPC_BIT8(0)
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#define TM_QW3_NSR_HE PPC_BITMASK8(0,1)
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#define TM_QW3_NSR_HE_NONE 0
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#define TM_QW3_NSR_HE_POOL 1
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#define TM_QW3_NSR_HE_PHYS 2
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#define TM_QW3_NSR_HE_LSI 3
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#define TM_QW3_NSR_I PPC_BIT8(2)
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#define TM_QW3_NSR_GRP_LVL PPC_BIT8(3,7)
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/* Utilities to manipulate these (originaly from OPAL) */
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#define MASK_TO_LSH(m) (__builtin_ffsl(m) - 1)
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#define GETFIELD(m, v) (((v) & (m)) >> MASK_TO_LSH(m))
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#define SETFIELD(m, v, val) \
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(((v) & ~(m)) | ((((typeof(v))(val)) << MASK_TO_LSH(m)) & (m)))
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#endif /* _ASM_POWERPC_XIVE_REGS_H */

‎arch/powerpc/include/asm/xive.h

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/*
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* Copyright 2016,2017 IBM Corporation.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#ifndef _ASM_POWERPC_XIVE_H
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#define _ASM_POWERPC_XIVE_H
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#define XIVE_INVALID_VP 0xffffffff
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#ifdef CONFIG_PPC_XIVE
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/*
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* Thread Interrupt Management Area (TIMA)
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*
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* This is a global MMIO region divided in 4 pages of varying access
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* permissions, providing access to per-cpu interrupt management
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* functions. It always identifies the CPU doing the access based
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* on the PowerBus initiator ID, thus we always access via the
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* same offset regardless of where the code is executing
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*/
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extern void __iomem *xive_tima;
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/*
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* Offset in the TM area of our current execution level (provided by
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* the backend)
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*/
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extern u32 xive_tima_offset;
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/*
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* Per-irq data (irq_get_handler_data for normal IRQs), IPIs
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* have it stored in the xive_cpu structure. We also cache
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* for normal interrupts the current target CPU.
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*
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* This structure is setup by the backend for each interrupt.
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*/
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struct xive_irq_data {
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u64 flags;
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u64 eoi_page;
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void __iomem *eoi_mmio;
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u64 trig_page;
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void __iomem *trig_mmio;
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u32 esb_shift;
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int src_chip;
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/* Setup/used by frontend */
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int target;
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bool saved_p;
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};
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#define XIVE_IRQ_FLAG_STORE_EOI 0x01
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#define XIVE_IRQ_FLAG_LSI 0x02
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#define XIVE_IRQ_FLAG_SHIFT_BUG 0x04
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#define XIVE_IRQ_FLAG_MASK_FW 0x08
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#define XIVE_IRQ_FLAG_EOI_FW 0x10
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#define XIVE_INVALID_CHIP_ID -1
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/* A queue tracking structure in a CPU */
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struct xive_q {
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__be32 *qpage;
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u32 msk;
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u32 idx;
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u32 toggle;
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u64 eoi_phys;
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u32 esc_irq;
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atomic_t count;
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atomic_t pending_count;
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};
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/*
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* "magic" Event State Buffer (ESB) MMIO offsets.
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*
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* Each interrupt source has a 2-bit state machine called ESB
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* which can be controlled by MMIO. It's made of 2 bits, P and
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* Q. P indicates that an interrupt is pending (has been sent
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* to a queue and is waiting for an EOI). Q indicates that the
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* interrupt has been triggered while pending.
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*
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* This acts as a coalescing mechanism in order to guarantee
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* that a given interrupt only occurs at most once in a queue.
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*
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* When doing an EOI, the Q bit will indicate if the interrupt
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* needs to be re-triggered.
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*
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* The following offsets into the ESB MMIO allow to read or
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* manipulate the PQ bits. They must be used with an 8-bytes
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* load instruction. They all return the previous state of the
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* interrupt (atomically).
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*
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* Additionally, some ESB pages support doing an EOI via a
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* store at 0 and some ESBs support doing a trigger via a
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* separate trigger page.
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*/
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#define XIVE_ESB_GET 0x800
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#define XIVE_ESB_SET_PQ_00 0xc00
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#define XIVE_ESB_SET_PQ_01 0xd00
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#define XIVE_ESB_SET_PQ_10 0xe00
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#define XIVE_ESB_SET_PQ_11 0xf00
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#define XIVE_ESB_MASK XIVE_ESB_SET_PQ_01
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#define XIVE_ESB_VAL_P 0x2
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#define XIVE_ESB_VAL_Q 0x1
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/* Global enable flags for the XIVE support */
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extern bool __xive_enabled;
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static inline bool xive_enabled(void) { return __xive_enabled; }
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extern bool xive_native_init(void);
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extern void xive_smp_probe(void);
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extern int xive_smp_prepare_cpu(unsigned int cpu);
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extern void xive_smp_setup_cpu(void);
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extern void xive_smp_disable_cpu(void);
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extern void xive_kexec_teardown_cpu(int secondary);
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extern void xive_shutdown(void);
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extern void xive_flush_interrupt(void);
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/* xmon hook */
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extern void xmon_xive_do_dump(int cpu);
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/* APIs used by KVM */
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extern u32 xive_native_default_eq_shift(void);
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extern u32 xive_native_alloc_vp_block(u32 max_vcpus);
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extern void xive_native_free_vp_block(u32 vp_base);
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extern int xive_native_populate_irq_data(u32 hw_irq,
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struct xive_irq_data *data);
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extern void xive_cleanup_irq_data(struct xive_irq_data *xd);
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extern u32 xive_native_alloc_irq(void);
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extern void xive_native_free_irq(u32 irq);
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extern int xive_native_configure_irq(u32 hw_irq, u32 target, u8 prio, u32 sw_irq);
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extern int xive_native_configure_queue(u32 vp_id, struct xive_q *q, u8 prio,
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__be32 *qpage, u32 order, bool can_escalate);
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extern void xive_native_disable_queue(u32 vp_id, struct xive_q *q, u8 prio);
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extern bool __xive_irq_trigger(struct xive_irq_data *xd);
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extern bool __xive_irq_retrigger(struct xive_irq_data *xd);
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extern void xive_do_source_eoi(u32 hw_irq, struct xive_irq_data *xd);
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extern bool is_xive_irq(struct irq_chip *chip);
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#else
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static inline bool xive_enabled(void) { return false; }
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static inline bool xive_native_init(void) { return false; }
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static inline void xive_smp_probe(void) { }
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extern inline int xive_smp_prepare_cpu(unsigned int cpu) { return -EINVAL; }
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static inline void xive_smp_setup_cpu(void) { }
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static inline void xive_smp_disable_cpu(void) { }
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static inline void xive_kexec_teardown_cpu(int secondary) { }
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static inline void xive_shutdown(void) { }
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static inline void xive_flush_interrupt(void) { }
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static inline u32 xive_native_alloc_vp_block(u32 max_vcpus) { return XIVE_INVALID_VP; }
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static inline void xive_native_free_vp_block(u32 vp_base) { }
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#endif
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#endif /* _ASM_POWERPC_XIVE_H */

‎arch/powerpc/include/asm/xmon.h

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@@ -29,5 +29,7 @@ static inline void xmon_register_spus(struct list_head *list) { };
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extern int cpus_are_in_xmon(void);
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#endif
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extern void xmon_printf(const char *format, ...);
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#endif /* __KERNEL __ */
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#endif /* __ASM_POWERPC_XMON_H */

‎arch/powerpc/kvm/book3s_hv_builtin.c

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@@ -23,6 +23,7 @@
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#include <asm/kvm_book3s.h>
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#include <asm/archrandom.h>
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#include <asm/xics.h>
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#include <asm/xive.h>
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#include <asm/dbell.h>
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#include <asm/cputhreads.h>
2829
#include <asm/io.h>
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224225
return;
225226
}
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228+
/* We should never reach this */
229+
if (WARN_ON_ONCE(xive_enabled()))
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return;
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227232
/* Else poke the target with an IPI */
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xics_phys = paca[cpu].kvm_hstate.xics_phys;
229234
if (xics_phys)
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386391
long rc;
387392
bool again;
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394+
if (xive_enabled())
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return 1;
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389397
do {
390398
again = false;
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rc = kvmppc_read_one_intr(&again);

‎arch/powerpc/platforms/powernv/Kconfig

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@@ -4,6 +4,7 @@ config PPC_POWERNV
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select PPC_NATIVE
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select PPC_XICS
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select PPC_ICP_NATIVE
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select PPC_XIVE_NATIVE
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select PPC_P7_NAP
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select PCI
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select PCI_MSI

‎arch/powerpc/platforms/powernv/setup.c

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@@ -32,6 +32,7 @@
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#include <asm/machdep.h>
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#include <asm/firmware.h>
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#include <asm/xics.h>
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#include <asm/xive.h>
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#include <asm/opal.h>
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#include <asm/kexec.h>
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#include <asm/smp.h>
@@ -76,7 +77,9 @@ static void __init pnv_init(void)
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7778
static void __init pnv_init_IRQ(void)
7879
{
79-
xics_init();
80+
/* Try using a XIVE if available, otherwise use a XICS */
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if (!xive_native_init())
82+
xics_init();
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WARN_ON(!ppc_md.get_irq);
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}
@@ -218,10 +221,12 @@ static void pnv_kexec_wait_secondaries_down(void)
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219222
static void pnv_kexec_cpu_down(int crash_shutdown, int secondary)
220223
{
221-
xics_kexec_teardown_cpu(secondary);
224+
if (xive_enabled())
225+
xive_kexec_teardown_cpu(secondary);
226+
else
227+
xics_kexec_teardown_cpu(secondary);
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/* On OPAL, we return all CPUs to firmware */
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if (!firmware_has_feature(FW_FEATURE_OPAL))
226231
return;
227232

@@ -237,6 +242,10 @@ static void pnv_kexec_cpu_down(int crash_shutdown, int secondary)
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/* Primary waits for the secondaries to have reached OPAL */
238243
pnv_kexec_wait_secondaries_down();
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/* Switch XIVE back to emulation mode */
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if (xive_enabled())
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xive_shutdown();
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/*
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* We might be running as little-endian - now that interrupts
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* are disabled, reset the HILE bit to big-endian so we don't

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