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Kan LiangPeter Zijlstra
Kan Liang
authored and
Peter Zijlstra
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perf/x86/intel: Fix unchecked MSR access error for Alder Lake N
For some Alder Lake N machine, the below unchecked MSR access error may be triggered. [ 0.088017] rcu: Hierarchical SRCU implementation. [ 0.088017] unchecked MSR access error: WRMSR to 0x38f (tried to write 0x0001000f0000003f) at rIP: 0xffffffffb5684de8 (native_write_msr+0x8/0x30) [ 0.088017] Call Trace: [ 0.088017] <TASK> [ 0.088017] __intel_pmu_enable_all.constprop.46+0x4a/0xa0 The Alder Lake N only has e-cores. The X86_FEATURE_HYBRID_CPU flag is not set. The perf cannot retrieve the correct CPU type via get_this_hybrid_cpu_type(). The model specific get_hybrid_cpu_type() is hardcode to p-core. The wrong CPU type is given to the PMU of the Alder Lake N. Since Alder Lake N isn't in fact a hybrid CPU, remove ALDERLAKE_N from the rest of {ALDER,RAPTOP}LAKE and create a non-hybrid PMU setup. The differences between Gracemont and the previous Tremont are, - Number of GP counters - Load and store latency Events - PEBS event_constraints - Instruction Latency support - Data source encoding - Memory access latency encoding Fixes: c2a960f ("perf/x86: Add new Alder Lake and Raptor Lake support") Reported-by: Jianfeng Gao <jianfeng.gao@intel.com> Suggested-by: Peter Zijlstra (Intel) <peterz@infradead.org> Signed-off-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lkml.kernel.org/r/20220831142702.153110-1-kan.liang@linux.intel.com
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‎arch/x86/events/intel/core.c

Lines changed: 39 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2102,6 +2102,15 @@ static struct extra_reg intel_tnt_extra_regs[] __read_mostly = {
21022102
EVENT_EXTRA_END
21032103
};
21042104

2105+
EVENT_ATTR_STR(mem-loads, mem_ld_grt, "event=0xd0,umask=0x5,ldlat=3");
2106+
EVENT_ATTR_STR(mem-stores, mem_st_grt, "event=0xd0,umask=0x6");
2107+
2108+
static struct attribute *grt_mem_attrs[] = {
2109+
EVENT_PTR(mem_ld_grt),
2110+
EVENT_PTR(mem_st_grt),
2111+
NULL
2112+
};
2113+
21052114
static struct extra_reg intel_grt_extra_regs[] __read_mostly = {
21062115
/* must define OFFCORE_RSP_X first, see intel_fixup_er() */
21072116
INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0),
@@ -5974,6 +5983,36 @@ __init int intel_pmu_init(void)
59745983
name = "Tremont";
59755984
break;
59765985

5986+
case INTEL_FAM6_ALDERLAKE_N:
5987+
x86_pmu.mid_ack = true;
5988+
memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,
5989+
sizeof(hw_cache_event_ids));
5990+
memcpy(hw_cache_extra_regs, tnt_hw_cache_extra_regs,
5991+
sizeof(hw_cache_extra_regs));
5992+
hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
5993+
5994+
x86_pmu.event_constraints = intel_slm_event_constraints;
5995+
x86_pmu.pebs_constraints = intel_grt_pebs_event_constraints;
5996+
x86_pmu.extra_regs = intel_grt_extra_regs;
5997+
5998+
x86_pmu.pebs_aliases = NULL;
5999+
x86_pmu.pebs_prec_dist = true;
6000+
x86_pmu.pebs_block = true;
6001+
x86_pmu.lbr_pt_coexist = true;
6002+
x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6003+
x86_pmu.flags |= PMU_FL_INSTR_LATENCY;
6004+
6005+
intel_pmu_pebs_data_source_grt();
6006+
x86_pmu.pebs_latency_data = adl_latency_data_small;
6007+
x86_pmu.get_event_constraints = tnt_get_event_constraints;
6008+
x86_pmu.limit_period = spr_limit_period;
6009+
td_attr = tnt_events_attrs;
6010+
mem_attr = grt_mem_attrs;
6011+
extra_attr = nhm_format_attr;
6012+
pr_cont("Gracemont events, ");
6013+
name = "gracemont";
6014+
break;
6015+
59776016
case INTEL_FAM6_WESTMERE:
59786017
case INTEL_FAM6_WESTMERE_EP:
59796018
case INTEL_FAM6_WESTMERE_EX:
@@ -6316,7 +6355,6 @@ __init int intel_pmu_init(void)
63166355

63176356
case INTEL_FAM6_ALDERLAKE:
63186357
case INTEL_FAM6_ALDERLAKE_L:
6319-
case INTEL_FAM6_ALDERLAKE_N:
63206358
case INTEL_FAM6_RAPTORLAKE:
63216359
case INTEL_FAM6_RAPTORLAKE_P:
63226360
/*

‎arch/x86/events/intel/ds.c

Lines changed: 7 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -110,13 +110,18 @@ void __init intel_pmu_pebs_data_source_skl(bool pmem)
110110
__intel_pmu_pebs_data_source_skl(pmem, pebs_data_source);
111111
}
112112

113-
static void __init intel_pmu_pebs_data_source_grt(u64 *data_source)
113+
static void __init __intel_pmu_pebs_data_source_grt(u64 *data_source)
114114
{
115115
data_source[0x05] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT);
116116
data_source[0x06] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM);
117117
data_source[0x08] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOPX, FWD);
118118
}
119119

120+
void __init intel_pmu_pebs_data_source_grt(void)
121+
{
122+
__intel_pmu_pebs_data_source_grt(pebs_data_source);
123+
}
124+
120125
void __init intel_pmu_pebs_data_source_adl(void)
121126
{
122127
u64 *data_source;
@@ -127,7 +132,7 @@ void __init intel_pmu_pebs_data_source_adl(void)
127132

128133
data_source = x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX].pebs_data_source;
129134
memcpy(data_source, pebs_data_source, sizeof(pebs_data_source));
130-
intel_pmu_pebs_data_source_grt(data_source);
135+
__intel_pmu_pebs_data_source_grt(data_source);
131136
}
132137

133138
static u64 precise_store_data(u64 status)

‎arch/x86/events/perf_event.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1516,6 +1516,8 @@ void intel_pmu_pebs_data_source_skl(bool pmem);
15161516

15171517
void intel_pmu_pebs_data_source_adl(void);
15181518

1519+
void intel_pmu_pebs_data_source_grt(void);
1520+
15191521
int intel_pmu_setup_lbr_filter(struct perf_event *event);
15201522

15211523
void intel_pt_interrupt(void);

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