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mlankhorstmlankhorst
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drm/i915: Do not rely on wm preservation for ILK watermarks
The original intent was to preserve watermarks as much as possible in intel_pipe_wm.raw_wm, and put the validated ones in intel_pipe_wm.wm. It seems this approach is insufficient and we don't always preserve the raw watermarks, so just use the atomic iterator we're already using to get a const pointer to all bound planes on the crtc. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102373 Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: stable@vger.kernel.org #v4.8+ Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171019151341.4579-1-maarten.lankhorst@linux.intel.com
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-31
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+21
-31
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‎drivers/gpu/drm/i915/intel_drv.h

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -501,7 +501,6 @@ struct intel_crtc_scaler_state {
501501

502502
struct intel_pipe_wm {
503503
struct intel_wm_level wm[5];
504-
struct intel_wm_level raw_wm[5];
505504
uint32_t linetime;
506505
bool fbc_wm_enabled;
507506
bool pipe_enabled;

‎drivers/gpu/drm/i915/intel_pm.c

Lines changed: 21 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -2721,9 +2721,9 @@ static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
27212721
const struct intel_crtc *intel_crtc,
27222722
int level,
27232723
struct intel_crtc_state *cstate,
2724-
struct intel_plane_state *pristate,
2725-
struct intel_plane_state *sprstate,
2726-
struct intel_plane_state *curstate,
2724+
const struct intel_plane_state *pristate,
2725+
const struct intel_plane_state *sprstate,
2726+
const struct intel_plane_state *curstate,
27272727
struct intel_wm_level *result)
27282728
{
27292729
uint16_t pri_latency = dev_priv->wm.pri_latency[level];
@@ -3043,28 +3043,24 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
30433043
struct intel_pipe_wm *pipe_wm;
30443044
struct drm_device *dev = state->dev;
30453045
const struct drm_i915_private *dev_priv = to_i915(dev);
3046-
struct intel_plane *intel_plane;
3047-
struct intel_plane_state *pristate = NULL;
3048-
struct intel_plane_state *sprstate = NULL;
3049-
struct intel_plane_state *curstate = NULL;
3046+
struct drm_plane *plane;
3047+
const struct drm_plane_state *plane_state;
3048+
const struct intel_plane_state *pristate = NULL;
3049+
const struct intel_plane_state *sprstate = NULL;
3050+
const struct intel_plane_state *curstate = NULL;
30503051
int level, max_level = ilk_wm_max_level(dev_priv), usable_level;
30513052
struct ilk_wm_maximums max;
30523053

30533054
pipe_wm = &cstate->wm.ilk.optimal;
30543055

3055-
for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3056-
struct intel_plane_state *ps;
3057-
3058-
ps = intel_atomic_get_existing_plane_state(state,
3059-
intel_plane);
3060-
if (!ps)
3061-
continue;
3056+
drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, &cstate->base) {
3057+
const struct intel_plane_state *ps = to_intel_plane_state(plane_state);
30623058

3063-
if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
3059+
if (plane->type == DRM_PLANE_TYPE_PRIMARY)
30643060
pristate = ps;
3065-
else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
3061+
else if (plane->type == DRM_PLANE_TYPE_OVERLAY)
30663062
sprstate = ps;
3067-
else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
3063+
else if (plane->type == DRM_PLANE_TYPE_CURSOR)
30683064
curstate = ps;
30693065
}
30703066

@@ -3086,11 +3082,9 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
30863082
if (pipe_wm->sprites_scaled)
30873083
usable_level = 0;
30883084

3089-
ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
3090-
pristate, sprstate, curstate, &pipe_wm->raw_wm[0]);
3091-
30923085
memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
3093-
pipe_wm->wm[0] = pipe_wm->raw_wm[0];
3086+
ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
3087+
pristate, sprstate, curstate, &pipe_wm->wm[0]);
30943088

30953089
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
30963090
pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
@@ -3100,8 +3094,8 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
31003094

31013095
ilk_compute_wm_reg_maximums(dev_priv, 1, &max);
31023096

3103-
for (level = 1; level <= max_level; level++) {
3104-
struct intel_wm_level *wm = &pipe_wm->raw_wm[level];
3097+
for (level = 1; level <= usable_level; level++) {
3098+
struct intel_wm_level *wm = &pipe_wm->wm[level];
31053099

31063100
ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
31073101
pristate, sprstate, curstate, wm);
@@ -3111,13 +3105,10 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
31113105
* register maximums since such watermarks are
31123106
* always invalid.
31133107
*/
3114-
if (level > usable_level)
3115-
continue;
3116-
3117-
if (ilk_validate_wm_level(level, &max, wm))
3118-
pipe_wm->wm[level] = *wm;
3119-
else
3120-
usable_level = level;
3108+
if (!ilk_validate_wm_level(level, &max, wm)) {
3109+
memset(wm, 0, sizeof(*wm));
3110+
break;
3111+
}
31213112
}
31223113

31233114
return 0;

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