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Ben Hutchings
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sfc: Allocate SRAM between buffer table and descriptor caches at init time
Each port has a block of 64-bit SRAM that is divided between buffer table and descriptor cache regions at initialisation time. Currently we use a fixed allocation, but it needs to be changed to support larger numbers of queues. Signed-off-by: Ben Hutchings <bhutchings@solarflare.com>
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6 files changed

+50
-14
lines changed

6 files changed

+50
-14
lines changed

‎drivers/net/ethernet/sfc/efx.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1420,6 +1420,8 @@ static int efx_probe_nic(struct efx_nic *efx)
14201420
if (rc)
14211421
goto fail;
14221422

1423+
efx->type->dimension_resources(efx);
1424+
14231425
if (efx->n_channels > 1)
14241426
get_random_bytes(&efx->rx_hash_key, sizeof(efx->rx_hash_key));
14251427
for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); i++)

‎drivers/net/ethernet/sfc/falcon.c

Lines changed: 8 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1333,6 +1333,12 @@ static int falcon_probe_nvconfig(struct efx_nic *efx)
13331333
return rc;
13341334
}
13351335

1336+
static void falcon_dimension_resources(struct efx_nic *efx)
1337+
{
1338+
efx->rx_dc_base = 0x20000;
1339+
efx->tx_dc_base = 0x26000;
1340+
}
1341+
13361342
/* Probe all SPI devices on the NIC */
13371343
static void falcon_probe_spi_devices(struct efx_nic *efx)
13381344
{
@@ -1749,6 +1755,7 @@ const struct efx_nic_type falcon_a1_nic_type = {
17491755
.probe = falcon_probe_nic,
17501756
.remove = falcon_remove_nic,
17511757
.init = falcon_init_nic,
1758+
.dimension_resources = falcon_dimension_resources,
17521759
.fini = efx_port_dummy_op_void,
17531760
.monitor = falcon_monitor,
17541761
.map_reset_reason = falcon_map_reset_reason,
@@ -1783,15 +1790,14 @@ const struct efx_nic_type falcon_a1_nic_type = {
17831790
.max_interrupt_mode = EFX_INT_MODE_MSI,
17841791
.phys_addr_channels = 4,
17851792
.timer_period_max = 1 << FRF_AB_TC_TIMER_VAL_WIDTH,
1786-
.tx_dc_base = 0x130000,
1787-
.rx_dc_base = 0x100000,
17881793
.offload_features = NETIF_F_IP_CSUM,
17891794
};
17901795

17911796
const struct efx_nic_type falcon_b0_nic_type = {
17921797
.probe = falcon_probe_nic,
17931798
.remove = falcon_remove_nic,
17941799
.init = falcon_init_nic,
1800+
.dimension_resources = falcon_dimension_resources,
17951801
.fini = efx_port_dummy_op_void,
17961802
.monitor = falcon_monitor,
17971803
.map_reset_reason = falcon_map_reset_reason,
@@ -1835,8 +1841,6 @@ const struct efx_nic_type falcon_b0_nic_type = {
18351841
* interrupt handler only supports 32
18361842
* channels */
18371843
.timer_period_max = 1 << FRF_AB_TC_TIMER_VAL_WIDTH,
1838-
.tx_dc_base = 0x130000,
1839-
.rx_dc_base = 0x100000,
18401844
.offload_features = NETIF_F_IP_CSUM | NETIF_F_RXHASH | NETIF_F_NTUPLE,
18411845
};
18421846

‎drivers/net/ethernet/sfc/net_driver.h

Lines changed: 9 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -658,6 +658,9 @@ struct efx_filter_state;
658658
* should be allocated for this NIC
659659
* @rxq_entries: Size of receive queues requested by user.
660660
* @txq_entries: Size of transmit queues requested by user.
661+
* @tx_dc_base: Base qword address in SRAM of TX queue descriptor caches
662+
* @rx_dc_base: Base qword address in SRAM of RX queue descriptor caches
663+
* @sram_lim_qw: Qword address limit of SRAM
661664
* @next_buffer_table: First available buffer table id
662665
* @n_channels: Number of channels in use
663666
* @n_rx_channels: Number of channels used for RX (= number of RX queues)
@@ -753,6 +756,9 @@ struct efx_nic {
753756

754757
unsigned rxq_entries;
755758
unsigned txq_entries;
759+
unsigned tx_dc_base;
760+
unsigned rx_dc_base;
761+
unsigned sram_lim_qw;
756762
unsigned next_buffer_table;
757763
unsigned n_channels;
758764
unsigned n_rx_channels;
@@ -839,6 +845,8 @@ static inline unsigned int efx_port_num(struct efx_nic *efx)
839845
* @probe: Probe the controller
840846
* @remove: Free resources allocated by probe()
841847
* @init: Initialise the controller
848+
* @dimension_resources: Dimension controller resources (buffer table,
849+
* and VIs once the available interrupt resources are clear)
842850
* @fini: Shut down the controller
843851
* @monitor: Periodic function for polling link state and hardware monitor
844852
* @map_reset_reason: Map ethtool reset reason to a reset method
@@ -878,15 +886,14 @@ static inline unsigned int efx_port_num(struct efx_nic *efx)
878886
* @phys_addr_channels: Number of channels with physically addressed
879887
* descriptors
880888
* @timer_period_max: Maximum period of interrupt timer (in ticks)
881-
* @tx_dc_base: Base address in SRAM of TX queue descriptor caches
882-
* @rx_dc_base: Base address in SRAM of RX queue descriptor caches
883889
* @offload_features: net_device feature flags for protocol offload
884890
* features implemented in hardware
885891
*/
886892
struct efx_nic_type {
887893
int (*probe)(struct efx_nic *efx);
888894
void (*remove)(struct efx_nic *efx);
889895
int (*init)(struct efx_nic *efx);
896+
void (*dimension_resources)(struct efx_nic *efx);
890897
void (*fini)(struct efx_nic *efx);
891898
void (*monitor)(struct efx_nic *efx);
892899
enum reset_type (*map_reset_reason)(enum reset_type reason);
@@ -923,8 +930,6 @@ struct efx_nic_type {
923930
unsigned int max_interrupt_mode;
924931
unsigned int phys_addr_channels;
925932
unsigned int timer_period_max;
926-
unsigned int tx_dc_base;
927-
unsigned int rx_dc_base;
928933
netdev_features_t offload_features;
929934
};
930935

‎drivers/net/ethernet/sfc/nic.c

Lines changed: 19 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1609,6 +1609,23 @@ void efx_nic_fini_interrupt(struct efx_nic *efx)
16091609
free_irq(efx->legacy_irq, efx);
16101610
}
16111611

1612+
void efx_nic_dimension_resources(struct efx_nic *efx, unsigned sram_lim_qw)
1613+
{
1614+
unsigned vi_count, buftbl_min;
1615+
1616+
/* Account for the buffer table entries backing the datapath channels
1617+
* and the descriptor caches for those channels.
1618+
*/
1619+
buftbl_min = ((efx->n_rx_channels * EFX_MAX_DMAQ_SIZE +
1620+
efx->n_tx_channels * EFX_TXQ_TYPES * EFX_MAX_DMAQ_SIZE +
1621+
efx->n_channels * EFX_MAX_EVQ_SIZE)
1622+
* sizeof(efx_qword_t) / EFX_BUF_SIZE);
1623+
vi_count = max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES);
1624+
1625+
efx->tx_dc_base = sram_lim_qw - vi_count * TX_DC_ENTRIES;
1626+
efx->rx_dc_base = efx->tx_dc_base - vi_count * RX_DC_ENTRIES;
1627+
}
1628+
16121629
u32 efx_nic_fpga_ver(struct efx_nic *efx)
16131630
{
16141631
efx_oword_t altera_build;
@@ -1621,11 +1638,9 @@ void efx_nic_init_common(struct efx_nic *efx)
16211638
efx_oword_t temp;
16221639

16231640
/* Set positions of descriptor caches in SRAM. */
1624-
EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_TX_DC_BASE_ADR,
1625-
efx->type->tx_dc_base / 8);
1641+
EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_TX_DC_BASE_ADR, efx->tx_dc_base);
16261642
efx_writeo(efx, &temp, FR_AZ_SRM_TX_DC_CFG);
1627-
EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_RX_DC_BASE_ADR,
1628-
efx->type->rx_dc_base / 8);
1643+
EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_RX_DC_BASE_ADR, efx->rx_dc_base);
16291644
efx_writeo(efx, &temp, FR_AZ_SRM_RX_DC_CFG);
16301645

16311646
/* Set TX descriptor cache size. */

‎drivers/net/ethernet/sfc/nic.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -230,6 +230,8 @@ extern void falcon_start_nic_stats(struct efx_nic *efx);
230230
extern void falcon_stop_nic_stats(struct efx_nic *efx);
231231
extern void falcon_setup_xaui(struct efx_nic *efx);
232232
extern int falcon_reset_xaui(struct efx_nic *efx);
233+
extern void
234+
efx_nic_dimension_resources(struct efx_nic *efx, unsigned sram_lim_qw);
233235
extern void efx_nic_init_common(struct efx_nic *efx);
234236
extern void efx_nic_push_rx_indir_table(struct efx_nic *efx);
235237

‎drivers/net/ethernet/sfc/siena.c

Lines changed: 10 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -225,6 +225,15 @@ static int siena_probe_nvconfig(struct efx_nic *efx)
225225
return rc;
226226
}
227227

228+
static void siena_dimension_resources(struct efx_nic *efx)
229+
{
230+
/* Each port has a small block of internal SRAM dedicated to
231+
* the buffer table and descriptor caches. In theory we can
232+
* map both blocks to one port, but we don't.
233+
*/
234+
efx_nic_dimension_resources(efx, FR_CZ_BUF_FULL_TBL_ROWS / 2);
235+
}
236+
228237
static int siena_probe_nic(struct efx_nic *efx)
229238
{
230239
struct siena_nic_data *nic_data;
@@ -619,6 +628,7 @@ const struct efx_nic_type siena_a0_nic_type = {
619628
.probe = siena_probe_nic,
620629
.remove = siena_remove_nic,
621630
.init = siena_init_nic,
631+
.dimension_resources = siena_dimension_resources,
622632
.fini = efx_port_dummy_op_void,
623633
.monitor = NULL,
624634
.map_reset_reason = siena_map_reset_reason,
@@ -657,8 +667,6 @@ const struct efx_nic_type siena_a0_nic_type = {
657667
* interrupt handler only supports 32
658668
* channels */
659669
.timer_period_max = 1 << FRF_CZ_TC_TIMER_VAL_WIDTH,
660-
.tx_dc_base = 0x88000,
661-
.rx_dc_base = 0x68000,
662670
.offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
663671
NETIF_F_RXHASH | NETIF_F_NTUPLE),
664672
};

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