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Merge tag 'kvm-s390-master-6.0-1' of git://git.kernel.org/pub/scm/linux/kernel/git/kvms390/linux into HEAD
PCI interpretation compile fixes
2 parents 35906d2 + ca922fe commit 29250ba

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‎.get_maintainer.ignore

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Alan Cox <alan@lxorguk.ukuu.org.uk>
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Alan Cox <root@hraefn.swansea.linux.org.uk>
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Christoph Hellwig <hch@lst.de>
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Marc Gonzalez <marc.w.gonzalez@free.fr>

‎.mailmap

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@@ -98,8 +98,7 @@ Christian Brauner <brauner@kernel.org> <christian.brauner@ubuntu.com>
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Christian Marangi <ansuelsmth@gmail.com>
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Christophe Ricard <christophe.ricard@gmail.com>
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Christoph Hellwig <hch@lst.de>
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Colin Ian King <colin.king@intel.com> <colin.king@canonical.com>
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Colin Ian King <colin.king@intel.com> <colin.i.king@gmail.com>
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Colin Ian King <colin.i.king@gmail.com> <colin.king@canonical.com>
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Corey Minyard <minyard@acm.org>
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Damian Hobson-Garcia <dhobsong@igel.co.jp>
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Daniel Borkmann <daniel@iogearbox.net> <danborkmann@googlemail.com>
@@ -150,6 +149,8 @@ Greg Kroah-Hartman <gregkh@suse.de>
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Greg Kroah-Hartman <greg@kroah.com>
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Greg Kurz <groug@kaod.org> <gkurz@linux.vnet.ibm.com>
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Gregory CLEMENT <gregory.clement@bootlin.com> <gregory.clement@free-electrons.com>
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Guilherme G. Piccoli <kernel@gpiccoli.net> <gpiccoli@linux.vnet.ibm.com>
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Guilherme G. Piccoli <kernel@gpiccoli.net> <gpiccoli@canonical.com>
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Guo Ren <guoren@kernel.org> <guoren@linux.alibaba.com>
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Guo Ren <guoren@kernel.org> <ren_guo@c-sky.com>
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Gustavo Padovan <gustavo@las.ic.unicamp.br>
@@ -253,6 +254,7 @@ Linus Lüssing <linus.luessing@c0d3.blue> <linus.luessing@web.de>
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Li Yang <leoyang.li@nxp.com> <leoli@freescale.com>
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Li Yang <leoyang.li@nxp.com> <leo@zh-kernel.org>
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Lorenzo Pieralisi <lpieralisi@kernel.org> <lorenzo.pieralisi@arm.com>
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Luca Ceresoli <luca.ceresoli@bootlin.com> <luca@lucaceresoli.net>
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Lukasz Luba <lukasz.luba@arm.com> <l.luba@partner.samsung.com>
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Maciej W. Rozycki <macro@mips.com> <macro@imgtec.com>
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Maciej W. Rozycki <macro@orcam.me.uk> <macro@linux-mips.org>

‎Documentation/ABI/testing/sysfs-devices-system-cpu

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@@ -523,6 +523,7 @@ What: /sys/devices/system/cpu/vulnerabilities
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/sys/devices/system/cpu/vulnerabilities/tsx_async_abort
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/sys/devices/system/cpu/vulnerabilities/itlb_multihit
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/sys/devices/system/cpu/vulnerabilities/mmio_stale_data
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/sys/devices/system/cpu/vulnerabilities/retbleed
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Date: January 2018
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Contact: Linux kernel mailing list <linux-kernel@vger.kernel.org>
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Description: Information about CPU vulnerabilities

‎Documentation/admin-guide/hw-vuln/processor_mmio_stale_data.rst

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@@ -230,6 +230,20 @@ The possible values in this file are:
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* - 'Mitigation: Clear CPU buffers'
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- The processor is vulnerable and the CPU buffer clearing mitigation is
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enabled.
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* - 'Unknown: No mitigations'
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- The processor vulnerability status is unknown because it is
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out of Servicing period. Mitigation is not attempted.
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Definitions:
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------------
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Servicing period: The process of providing functional and security updates to
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Intel processors or platforms, utilizing the Intel Platform Update (IPU)
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process or other similar mechanisms.
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End of Servicing Updates (ESU): ESU is the date at which Intel will no
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longer provide Servicing, such as through IPU or other similar update
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processes. ESU dates will typically be aligned to end of quarter.
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If the processor is vulnerable then the following information is appended to
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the above information:

‎Documentation/admin-guide/kernel-parameters.txt

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rodata= [KNL]
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on Mark read-only kernel memory as read-only (default).
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off Leave read-only kernel memory writable for debugging.
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full Mark read-only kernel memory and aliases as read-only
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[arm64]
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rockchip.usb_uart
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Enable the uart passthrough on the designated usb port

‎Documentation/admin-guide/sysctl/net.rst

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@@ -271,7 +271,7 @@ poll cycle or the number of packets processed reaches netdev_budget.
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netdev_max_backlog
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------------------
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Maximum number of packets, queued on the INPUT side, when the interface
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Maximum number of packets, queued on the INPUT side, when the interface
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receives packets faster than kernel can process them.
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netdev_rss_key

‎Documentation/arm64/elf_hwcaps.rst

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by Documentation/arm64/memory-tagging-extension.rst.
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HWCAP2_SME
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Functionality implied by ID_AA64PFR1_EL1.SME == 0b0001, as described
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by Documentation/arm64/sme.rst.
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HWCAP2_SME_I16I64
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Functionality implied by ID_AA64SMFR0_EL1.I16I64 == 0b1111.
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HWCAP2_SME_F64F64
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Functionality implied by ID_AA64SMFR0_EL1.F64F64 == 0b1.
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HWCAP2_SME_I8I32
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Functionality implied by ID_AA64SMFR0_EL1.I8I32 == 0b1111.
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HWCAP2_SME_F16F32
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Functionality implied by ID_AA64SMFR0_EL1.F16F32 == 0b1.
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HWCAP2_SME_B16F32
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Functionality implied by ID_AA64SMFR0_EL1.B16F32 == 0b1.
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HWCAP2_SME_F32F32
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Functionality implied by ID_AA64SMFR0_EL1.F32F32 == 0b1.
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HWCAP2_SME_FA64
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Functionality implied by ID_AA64SMFR0_EL1.FA64 == 0b1.
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HWCAP2_WFXT
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Functionality implied by ID_AA64ISAR2_EL1.WFXT == 0b0010.
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HWCAP2_EBF16
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4. Unused AT_HWCAP bits

‎Documentation/arm64/silicon-errata.rst

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| Allwinner | A64/R18 | UNKNOWN1 | SUN50I_ERRATUM_UNKNOWN1 |
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+----------------+-----------------+-----------------+-----------------------------+
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A510 | #2457168 | ARM64_ERRATUM_2457168 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A510 | #2064142 | ARM64_ERRATUM_2064142 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A510 | #2038923 | ARM64_ERRATUM_2038923 |

‎Documentation/atomic_bitops.txt

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- RMW operations that have a return value are fully ordered.
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- RMW operations that are conditional are unordered on FAILURE,
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otherwise the above rules apply. In the case of test_and_{}_bit() operations,
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if the bit in memory is unchanged by the operation then it is deemed to have
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failed.
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- RMW operations that are conditional are fully ordered.
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Except for a successful test_and_set_bit_lock() which has ACQUIRE semantics and
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clear_bit_unlock() which has RELEASE semantics.
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Except for a successful test_and_set_bit_lock() which has ACQUIRE semantics,
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clear_bit_unlock() which has RELEASE semantics and test_bit_acquire which has
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ACQUIRE semantics.
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Since a platform only has a single means of achieving atomic operations
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the same barriers as for atomic_t are used, see atomic_t.txt.

‎Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tcon.yaml

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- allwinner,sun8i-a83t-tcon-lcd
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- allwinner,sun8i-v3s-tcon
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- allwinner,sun9i-a80-tcon-lcd
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- allwinner,sun20i-d1-tcon-lcd
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then:
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properties:
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- allwinner,sun8i-a83t-tcon-tv
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- allwinner,sun8i-r40-tcon-tv
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- allwinner,sun9i-a80-tcon-tv
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- allwinner,sun20i-d1-tcon-tv
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then:
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properties:
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- allwinner,sun9i-a80-tcon-lcd
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- allwinner,sun4i-a10-tcon
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- allwinner,sun8i-a83t-tcon-lcd
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- allwinner,sun20i-d1-tcon-lcd
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then:
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required:
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- allwinner,sun8i-a23-tcon
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- allwinner,sun8i-a33-tcon
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- allwinner,sun8i-a83t-tcon-lcd
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- allwinner,sun20i-d1-tcon-lcd
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then:
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properties:

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