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153 | 153 | # define LAN9303_SWE_VLAN_UNTAG_PORT0 BIT(12)
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154 | 154 | #define LAN9303_SWE_VLAN_CMD_STS 0x1810
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155 | 155 | #define LAN9303_SWE_GLB_INGRESS_CFG 0x1840
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| 156 | +# define LAN9303_SWE_GLB_INGR_IGMP_TRAP BIT(7) |
| 157 | +# define LAN9303_SWE_GLB_INGR_IGMP_PORT(p) BIT(10 + p) |
156 | 158 | #define LAN9303_SWE_PORT_STATE 0x1843
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157 | 159 | # define LAN9303_SWE_PORT_STATE_FORWARDING_PORT2 (0)
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158 | 160 | # define LAN9303_SWE_PORT_STATE_LEARNING_PORT2 BIT(5)
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@@ -450,6 +452,21 @@ static int lan9303_read_switch_reg(struct lan9303 *chip, u16 regnum, u32 *val)
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450 | 452 | return ret;
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451 | 453 | }
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452 | 454 |
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| 455 | +static int lan9303_write_switch_reg_mask(struct lan9303 *chip, u16 regnum, |
| 456 | + u32 val, u32 mask) |
| 457 | +{ |
| 458 | + int ret; |
| 459 | + u32 reg; |
| 460 | + |
| 461 | + ret = lan9303_read_switch_reg(chip, regnum, ®); |
| 462 | + if (ret) |
| 463 | + return ret; |
| 464 | + |
| 465 | + reg = (reg & ~mask) | val; |
| 466 | + |
| 467 | + return lan9303_write_switch_reg(chip, regnum, reg); |
| 468 | +} |
| 469 | + |
453 | 470 | static int lan9303_write_switch_port(struct lan9303 *chip, int port,
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454 | 471 | u16 regnum, u32 val)
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455 | 472 | {
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@@ -905,6 +922,15 @@ static int lan9303_setup(struct dsa_switch *ds)
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905 | 922 | if (ret)
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906 | 923 | dev_err(chip->dev, "failed to re-enable switching %d\n", ret);
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907 | 924 |
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| 925 | + /* Trap IGMP to port 0 */ |
| 926 | + ret = lan9303_write_switch_reg_mask(chip, LAN9303_SWE_GLB_INGRESS_CFG, |
| 927 | + LAN9303_SWE_GLB_INGR_IGMP_TRAP | |
| 928 | + LAN9303_SWE_GLB_INGR_IGMP_PORT(0), |
| 929 | + LAN9303_SWE_GLB_INGR_IGMP_PORT(1) | |
| 930 | + LAN9303_SWE_GLB_INGR_IGMP_PORT(2)); |
| 931 | + if (ret) |
| 932 | + dev_err(chip->dev, "failed to setup IGMP trap %d\n", ret); |
| 933 | + |
908 | 934 | return 0;
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909 | 935 | }
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910 | 936 |
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