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Merge tag 'drm-intel-fixes-2016-08-15' of git://anongit.freedesktop.org/drm-intel into drm-fixes
Collection of i915 fixes. * tag 'drm-intel-fixes-2016-08-15' of git://anongit.freedesktop.org/drm-intel: drm/i915: Fix modeset handling during gpu reset, v5. drm/i915: fix aliasing_ppgtt leak drm/i915: fix WaInsertDummyPushConstPs drm/i915: Fix iboost setting for SKL Y/U DP DDI buffer translation entry 2 drm/i915/gen9: Give one extra block per line for SKL plane WM calculations drm/i915: Acquire audio powerwell for HD-Audio registers drm/i915: Add missing rpm wakelock to GGTT pread drm/i915/fbc: FBC causes display flicker when VT-d is enabled on Skylake drm/i915: Clean up the extra RPM ref on CHV with i915.enable_rc6=0 drm/i915: Program iboost settings for HDMI/DVI on SKL drm/i915: Fix iboost setting for DDI with 4 lanes on SKL drm/i915: Handle ENOSPC after failing to insert a mappable node drm/i915: Flush GT idle status upon reset
2 parents aae2d1f + dfa2997 commit 2c24ba2

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10 files changed

+219
-95
lines changed

10 files changed

+219
-95
lines changed

‎drivers/gpu/drm/i915/i915_drv.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1854,6 +1854,7 @@ struct drm_i915_private {
18541854
enum modeset_restore modeset_restore;
18551855
struct mutex modeset_restore_lock;
18561856
struct drm_atomic_state *modeset_restore_state;
1857+
struct drm_modeset_acquire_ctx reset_ctx;
18571858

18581859
struct list_head vm_list; /* Global list of all address spaces */
18591860
struct i915_ggtt ggtt; /* VM representing the global address space */

‎drivers/gpu/drm/i915/i915_gem.c

Lines changed: 8 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -879,9 +879,12 @@ i915_gem_pread_ioctl(struct drm_device *dev, void *data,
879879
ret = i915_gem_shmem_pread(dev, obj, args, file);
880880

881881
/* pread for non shmem backed objects */
882-
if (ret == -EFAULT || ret == -ENODEV)
882+
if (ret == -EFAULT || ret == -ENODEV) {
883+
intel_runtime_pm_get(to_i915(dev));
883884
ret = i915_gem_gtt_pread(dev, obj, args->size,
884885
args->offset, args->data_ptr);
886+
intel_runtime_pm_put(to_i915(dev));
887+
}
885888

886889
out:
887890
drm_gem_object_unreference(&obj->base);
@@ -1306,7 +1309,7 @@ i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
13061309
* textures). Fallback to the shmem path in that case. */
13071310
}
13081311

1309-
if (ret == -EFAULT) {
1312+
if (ret == -EFAULT || ret == -ENOSPC) {
13101313
if (obj->phys_handle)
13111314
ret = i915_gem_phys_pwrite(obj, args, file);
13121315
else if (i915_gem_object_has_struct_page(obj))
@@ -3169,6 +3172,8 @@ static void i915_gem_reset_engine_cleanup(struct intel_engine_cs *engine)
31693172
}
31703173

31713174
intel_ring_init_seqno(engine, engine->last_submitted_seqno);
3175+
3176+
engine->i915->gt.active_engines &= ~intel_engine_flag(engine);
31723177
}
31733178

31743179
void i915_gem_reset(struct drm_device *dev)
@@ -3186,6 +3191,7 @@ void i915_gem_reset(struct drm_device *dev)
31863191

31873192
for_each_engine(engine, dev_priv)
31883193
i915_gem_reset_engine_cleanup(engine);
3194+
mod_delayed_work(dev_priv->wq, &dev_priv->gt.idle_work, 0);
31893195

31903196
i915_gem_context_reset(dev);
31913197

‎drivers/gpu/drm/i915/i915_gem_gtt.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2873,6 +2873,7 @@ void i915_ggtt_cleanup_hw(struct drm_device *dev)
28732873
struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
28742874

28752875
ppgtt->base.cleanup(&ppgtt->base);
2876+
kfree(ppgtt);
28762877
}
28772878

28782879
i915_gem_cleanup_stolen(dev);

‎drivers/gpu/drm/i915/i915_reg.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1536,6 +1536,7 @@ enum skl_disp_power_wells {
15361536
#define BALANCE_LEG_MASK(port) (7<<(8+3*(port)))
15371537
/* Balance leg disable bits */
15381538
#define BALANCE_LEG_DISABLE_SHIFT 23
1539+
#define BALANCE_LEG_DISABLE(port) (1 << (23 + (port)))
15391540

15401541
/*
15411542
* Fence registers

‎drivers/gpu/drm/i915/intel_audio.c

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -600,6 +600,8 @@ static void i915_audio_component_codec_wake_override(struct device *dev,
600600
if (!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv))
601601
return;
602602

603+
i915_audio_component_get_power(dev);
604+
603605
/*
604606
* Enable/disable generating the codec wake signal, overriding the
605607
* internal logic to generate the codec wake to controller.
@@ -615,6 +617,8 @@ static void i915_audio_component_codec_wake_override(struct device *dev,
615617
I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
616618
usleep_range(1000, 1500);
617619
}
620+
621+
i915_audio_component_put_power(dev);
618622
}
619623

620624
/* Get CDCLK in kHz */
@@ -648,6 +652,7 @@ static int i915_audio_component_sync_audio_rate(struct device *dev,
648652
!IS_HASWELL(dev_priv))
649653
return 0;
650654

655+
i915_audio_component_get_power(dev);
651656
mutex_lock(&dev_priv->av_mutex);
652657
/* 1. get the pipe */
653658
intel_encoder = dev_priv->dig_port_map[port];
@@ -698,6 +703,7 @@ static int i915_audio_component_sync_audio_rate(struct device *dev,
698703

699704
unlock:
700705
mutex_unlock(&dev_priv->av_mutex);
706+
i915_audio_component_put_power(dev);
701707
return err;
702708
}
703709

‎drivers/gpu/drm/i915/intel_ddi.c

Lines changed: 65 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -145,7 +145,7 @@ static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
145145
static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
146146
{ 0x0000201B, 0x000000A2, 0x0 },
147147
{ 0x00005012, 0x00000088, 0x0 },
148-
{ 0x80007011, 0x000000CD, 0x0 },
148+
{ 0x80007011, 0x000000CD, 0x1 },
149149
{ 0x80009010, 0x000000C0, 0x1 },
150150
{ 0x0000201B, 0x0000009D, 0x0 },
151151
{ 0x80005012, 0x000000C0, 0x1 },
@@ -158,7 +158,7 @@ static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
158158
static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
159159
{ 0x00000018, 0x000000A2, 0x0 },
160160
{ 0x00005012, 0x00000088, 0x0 },
161-
{ 0x80007011, 0x000000CD, 0x0 },
161+
{ 0x80007011, 0x000000CD, 0x3 },
162162
{ 0x80009010, 0x000000C0, 0x3 },
163163
{ 0x00000018, 0x0000009D, 0x0 },
164164
{ 0x80005012, 0x000000C0, 0x3 },
@@ -388,6 +388,40 @@ skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
388388
}
389389
}
390390

391+
static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
392+
{
393+
int n_hdmi_entries;
394+
int hdmi_level;
395+
int hdmi_default_entry;
396+
397+
hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
398+
399+
if (IS_BROXTON(dev_priv))
400+
return hdmi_level;
401+
402+
if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
403+
skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
404+
hdmi_default_entry = 8;
405+
} else if (IS_BROADWELL(dev_priv)) {
406+
n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
407+
hdmi_default_entry = 7;
408+
} else if (IS_HASWELL(dev_priv)) {
409+
n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
410+
hdmi_default_entry = 6;
411+
} else {
412+
WARN(1, "ddi translation table missing\n");
413+
n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
414+
hdmi_default_entry = 7;
415+
}
416+
417+
/* Choose a good default if VBT is badly populated */
418+
if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
419+
hdmi_level >= n_hdmi_entries)
420+
hdmi_level = hdmi_default_entry;
421+
422+
return hdmi_level;
423+
}
424+
391425
/*
392426
* Starting with Haswell, DDI port buffers must be programmed with correct
393427
* values in advance. The buffer values are different for FDI and DP modes,
@@ -399,7 +433,7 @@ void intel_prepare_ddi_buffer(struct intel_encoder *encoder)
399433
{
400434
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
401435
u32 iboost_bit = 0;
402-
int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_default_entry,
436+
int i, n_hdmi_entries, n_dp_entries, n_edp_entries,
403437
size;
404438
int hdmi_level;
405439
enum port port;
@@ -410,7 +444,7 @@ void intel_prepare_ddi_buffer(struct intel_encoder *encoder)
410444
const struct ddi_buf_trans *ddi_translations;
411445

412446
port = intel_ddi_get_encoder_port(encoder);
413-
hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
447+
hdmi_level = intel_ddi_hdmi_level(dev_priv, port);
414448

415449
if (IS_BROXTON(dev_priv)) {
416450
if (encoder->type != INTEL_OUTPUT_HDMI)
@@ -430,7 +464,6 @@ void intel_prepare_ddi_buffer(struct intel_encoder *encoder)
430464
skl_get_buf_trans_edp(dev_priv, &n_edp_entries);
431465
ddi_translations_hdmi =
432466
skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
433-
hdmi_default_entry = 8;
434467
/* If we're boosting the current, set bit 31 of trans1 */
435468
if (dev_priv->vbt.ddi_port_info[port].hdmi_boost_level ||
436469
dev_priv->vbt.ddi_port_info[port].dp_boost_level)
@@ -456,15 +489,13 @@ void intel_prepare_ddi_buffer(struct intel_encoder *encoder)
456489

457490
n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
458491
n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
459-
hdmi_default_entry = 7;
460492
} else if (IS_HASWELL(dev_priv)) {
461493
ddi_translations_fdi = hsw_ddi_translations_fdi;
462494
ddi_translations_dp = hsw_ddi_translations_dp;
463495
ddi_translations_edp = hsw_ddi_translations_dp;
464496
ddi_translations_hdmi = hsw_ddi_translations_hdmi;
465497
n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
466498
n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
467-
hdmi_default_entry = 6;
468499
} else {
469500
WARN(1, "ddi translation table missing\n");
470501
ddi_translations_edp = bdw_ddi_translations_dp;
@@ -474,7 +505,6 @@ void intel_prepare_ddi_buffer(struct intel_encoder *encoder)
474505
n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
475506
n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
476507
n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
477-
hdmi_default_entry = 7;
478508
}
479509

480510
switch (encoder->type) {
@@ -505,11 +535,6 @@ void intel_prepare_ddi_buffer(struct intel_encoder *encoder)
505535
if (encoder->type != INTEL_OUTPUT_HDMI)
506536
return;
507537

508-
/* Choose a good default if VBT is badly populated */
509-
if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
510-
hdmi_level >= n_hdmi_entries)
511-
hdmi_level = hdmi_default_entry;
512-
513538
/* Entry 9 is for HDMI: */
514539
I915_WRITE(DDI_BUF_TRANS_LO(port, i),
515540
ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit);
@@ -1379,14 +1404,30 @@ void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
13791404
TRANS_CLK_SEL_DISABLED);
13801405
}
13811406

1382-
static void skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
1383-
u32 level, enum port port, int type)
1407+
static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
1408+
enum port port, uint8_t iboost)
13841409
{
1410+
u32 tmp;
1411+
1412+
tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
1413+
tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
1414+
if (iboost)
1415+
tmp |= iboost << BALANCE_LEG_SHIFT(port);
1416+
else
1417+
tmp |= BALANCE_LEG_DISABLE(port);
1418+
I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);
1419+
}
1420+
1421+
static void skl_ddi_set_iboost(struct intel_encoder *encoder, u32 level)
1422+
{
1423+
struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
1424+
struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
1425+
enum port port = intel_dig_port->port;
1426+
int type = encoder->type;
13851427
const struct ddi_buf_trans *ddi_translations;
13861428
uint8_t iboost;
13871429
uint8_t dp_iboost, hdmi_iboost;
13881430
int n_entries;
1389-
u32 reg;
13901431

13911432
/* VBT may override standard boost values */
13921433
dp_iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
@@ -1428,16 +1469,10 @@ static void skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
14281469
return;
14291470
}
14301471

1431-
reg = I915_READ(DISPIO_CR_TX_BMU_CR0);
1432-
reg &= ~BALANCE_LEG_MASK(port);
1433-
reg &= ~(1 << (BALANCE_LEG_DISABLE_SHIFT + port));
1434-
1435-
if (iboost)
1436-
reg |= iboost << BALANCE_LEG_SHIFT(port);
1437-
else
1438-
reg |= 1 << (BALANCE_LEG_DISABLE_SHIFT + port);
1472+
_skl_ddi_set_iboost(dev_priv, port, iboost);
14391473

1440-
I915_WRITE(DISPIO_CR_TX_BMU_CR0, reg);
1474+
if (port == PORT_A && intel_dig_port->max_lanes == 4)
1475+
_skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
14411476
}
14421477

14431478
static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
@@ -1568,7 +1603,7 @@ uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
15681603
level = translate_signal_level(signal_levels);
15691604

15701605
if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
1571-
skl_ddi_set_iboost(dev_priv, level, port, encoder->type);
1606+
skl_ddi_set_iboost(encoder, level);
15721607
else if (IS_BROXTON(dev_priv))
15731608
bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
15741609

@@ -1637,6 +1672,10 @@ static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
16371672
intel_dp_stop_link_train(intel_dp);
16381673
} else if (type == INTEL_OUTPUT_HDMI) {
16391674
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1675+
int level = intel_ddi_hdmi_level(dev_priv, port);
1676+
1677+
if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
1678+
skl_ddi_set_iboost(intel_encoder, level);
16401679

16411680
intel_hdmi->set_infoframes(encoder,
16421681
crtc->config->has_hdmi_sink,

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