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Merge tag 'v3.20-next-arm64' of https://github.com/mbgg/linux-mediatek into next/arm64
Merge "ARM: mediatek: arm64 changes for v3.20" from Matthias Brugger: Add support for mt8173 SoC from Mediatek. - add DT bindings documentation - add dts files for SoC and evaluation board - add to Kconfig and defconfig * tag 'v3.20-next-arm64' of https://github.com/mbgg/linux-mediatek: arm64: mediatek: Add MT8173 SoC Kconfig and defconfig arm64: dts: Add mediatek MT8173 SoC and evaluation board dts and Makefile Document: DT: Add bindings for mediatek MT8173 SoC Platform Signed-off-by: Olof Johansson <olof@lixom.net>
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‎Documentation/devicetree/bindings/arm/mediatek.txt

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@@ -9,6 +9,7 @@ compatible: Must contain one of
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"mediatek,mt6592"
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"mediatek,mt8127"
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"mediatek,mt8135"
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"mediatek,mt8173"
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Supported boards:
@@ -25,3 +26,6 @@ Supported boards:
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- MTK mt8135 tablet EVB:
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Required root node properties:
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- compatible = "mediatek,mt8135-evbp1", "mediatek,mt8135";
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- MTK mt8173 tablet EVB:
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Required root node properties:
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- compatible = "mediatek,mt8173-evb", "mediatek,mt8173";

‎Documentation/devicetree/bindings/arm/mediatek/mediatek,sysirq.txt

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@@ -5,6 +5,7 @@ interrupt.
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Required properties:
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- compatible: should be one of:
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"mediatek,mt8173-sysirq"
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"mediatek,mt8135-sysirq"
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"mediatek,mt8127-sysirq"
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"mediatek,mt6589-sysirq"

‎Documentation/devicetree/bindings/serial/mtk-uart.txt

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@@ -2,9 +2,11 @@
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Required properties:
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- compatible should contain:
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* "mediatek,mt8173-uart" for MT8173 compatible UARTS
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* "mediatek,mt6589-uart" for MT6589 compatible UARTS
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* "mediatek,mt6582-uart" for MT6582 compatible UARTS
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* "mediatek,mt6577-uart" for all compatible UARTS (MT6589, MT6582, MT6577)
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* "mediatek,mt6577-uart" for all compatible UARTS (MT8173, MT6589, MT6582,
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MT6577)
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- reg: The base address of the UART register bank.
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‎arch/arm64/Kconfig

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@@ -165,6 +165,12 @@ config ARCH_EXYNOS7
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help
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This enables support for Samsung Exynos7 SoC family
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config ARCH_MEDIATEK
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bool "Mediatek MT65xx & MT81xx ARMv8 SoC"
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select ARM_GIC
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help
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Support for Mediatek MT65xx & MT81xx ARMv8 SoCs
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config ARCH_SEATTLE
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bool "AMD Seattle SoC Family"
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help

‎arch/arm64/boot/dts/Makefile

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@@ -4,6 +4,7 @@ dts-dirs += arm
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dts-dirs += cavium
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dts-dirs += exynos
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dts-dirs += freescale
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dts-dirs += mediatek
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always := $(dtb-y)
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subdir-y := $(dts-dirs)

‎arch/arm64/boot/dts/mediatek/Makefile

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@@ -0,0 +1,5 @@
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
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always := $(dtb-y)
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subdir-y := $(dts-dirs)
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clean-files := *.dtb

‎arch/arm64/boot/dts/mediatek/mt8173-evb.dts

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@@ -0,0 +1,38 @@
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/*
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* Copyright (c) 2014 MediaTek Inc.
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* Author: Eddie Huang <eddie.huang@mediatek.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/dts-v1/;
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#include "mt8173.dtsi"
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/ {
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model = "mediatek,mt8173-evb";
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aliases {
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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serial3 = &uart3;
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};
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memory@40000000 {
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device_type = "memory";
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reg = <0 0x40000000 0 0x80000000>;
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};
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chosen { };
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};
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&uart0 {
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status = "okay";
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};

‎arch/arm64/boot/dts/mediatek/mt8173.dtsi

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/*
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* Copyright (c) 2014 MediaTek Inc.
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* Author: Eddie Huang <eddie.huang@mediatek.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "mediatek,mt8173";
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interrupt-parent = <&sysirq>;
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&cpu2>;
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};
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core1 {
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cpu = <&cpu3>;
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};
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};
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};
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x000>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x001>;
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enable-method = "psci";
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};
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cpu2: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x100>;
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enable-method = "psci";
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};
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cpu3: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x101>;
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enable-method = "psci";
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};
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};
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psci {
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compatible = "arm,psci";
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method = "smc";
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cpu_suspend = <0x84000001>;
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cpu_off = <0x84000002>;
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cpu_on = <0x84000003>;
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};
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uart_clk: dummy26m {
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compatible = "fixed-clock";
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clock-frequency = <26000000>;
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#clock-cells = <0>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 13
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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};
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "simple-bus";
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ranges;
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sysirq: intpol-controller@10200620 {
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compatible = "mediatek,mt8173-sysirq",
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"mediatek,mt6577-sysirq";
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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reg = <0 0x10200620 0 0x20>;
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};
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gic: interrupt-controller@10220000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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interrupt-controller;
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reg = <0 0x10221000 0 0x1000>,
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<0 0x10222000 0 0x2000>,
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<0 0x10224000 0 0x2000>,
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<0 0x10226000 0 0x2000>;
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interrupts = <GIC_PPI 9
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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uart0: serial@11002000 {
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compatible = "mediatek,mt8173-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11002000 0 0x400>;
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interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&uart_clk>;
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status = "disabled";
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};
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uart1: serial@11003000 {
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compatible = "mediatek,mt8173-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11003000 0 0x400>;
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interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&uart_clk>;
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status = "disabled";
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};
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uart2: serial@11004000 {
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compatible = "mediatek,mt8173-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11004000 0 0x400>;
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interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&uart_clk>;
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status = "disabled";
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};
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uart3: serial@11005000 {
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compatible = "mediatek,mt8173-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11005000 0 0x400>;
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interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&uart_clk>;
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status = "disabled";
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};
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};
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};
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‎arch/arm64/configs/defconfig

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@@ -32,6 +32,7 @@ CONFIG_MODULE_UNLOAD=y
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# CONFIG_BLK_DEV_BSG is not set
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# CONFIG_IOSCHED_DEADLINE is not set
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CONFIG_ARCH_FSL_LS2085A=y
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CONFIG_ARCH_MEDIATEK=y
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CONFIG_ARCH_THUNDER=y
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CONFIG_ARCH_VEXPRESS=y
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CONFIG_ARCH_XGENE=y
@@ -87,6 +88,7 @@ CONFIG_SERIO_AMBAKMI=y
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CONFIG_LEGACY_PTY_COUNT=16
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CONFIG_SERIAL_8250=y
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CONFIG_SERIAL_8250_CONSOLE=y
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CONFIG_SERIAL_8250_MT6577=y
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CONFIG_SERIAL_AMBA_PL011=y
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CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
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CONFIG_SERIAL_OF_PLATFORM=y

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