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torvaldstorvalds
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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin: Blackfin: bf52x/bf54x boards: drop unused nand page size Blackfin: punt duplicate SPORT MMR defines
2 parents 6b3a7c0 + 9e5610a commit 303fd2c

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-581
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13 files changed

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‎arch/blackfin/include/asm/bfin_sport.h

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -115,12 +115,6 @@ struct sport_register {
115115

116116
#endif
117117

118-
/* Workaround defBF*.h SPORT MMRs till they get cleansed */
119-
#undef DTYPE_NORM
120-
#undef SLEN
121-
#undef SP_WOFF
122-
#undef SP_WSIZE
123-
124118
/* SPORT_TCR1 Masks */
125119
#define TSPEN 0x0001 /* TX enable */
126120
#define ITCLK 0x0002 /* Internal TX Clock Select */

‎arch/blackfin/mach-bf518/include/mach/defBF51x_base.h

Lines changed: 0 additions & 82 deletions
Original file line numberDiff line numberDiff line change
@@ -913,88 +913,6 @@
913913
#define PH6 0x0040
914914
#define PH7 0x0080
915915

916-
917-
/* ******************* SERIAL PORT MASKS **************************************/
918-
/* SPORTx_TCR1 Masks */
919-
#define TSPEN 0x0001 /* Transmit Enable */
920-
#define ITCLK 0x0002 /* Internal Transmit Clock Select */
921-
#define DTYPE_NORM 0x0004 /* Data Format Normal */
922-
#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
923-
#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
924-
#define TLSBIT 0x0010 /* Transmit Bit Order */
925-
#define ITFS 0x0200 /* Internal Transmit Frame Sync Select */
926-
#define TFSR 0x0400 /* Transmit Frame Sync Required Select */
927-
#define DITFS 0x0800 /* Data-Independent Transmit Frame Sync Select */
928-
#define LTFS 0x1000 /* Low Transmit Frame Sync Select */
929-
#define LATFS 0x2000 /* Late Transmit Frame Sync Select */
930-
#define TCKFE 0x4000 /* Clock Falling Edge Select */
931-
932-
/* SPORTx_TCR2 Masks and Macro */
933-
#define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */
934-
#define TXSE 0x0100 /* TX Secondary Enable */
935-
#define TSFSE 0x0200 /* Transmit Stereo Frame Sync Enable */
936-
#define TRFST 0x0400 /* Left/Right Order (1 = Right Channel 1st) */
937-
938-
/* SPORTx_RCR1 Masks */
939-
#define RSPEN 0x0001 /* Receive Enable */
940-
#define IRCLK 0x0002 /* Internal Receive Clock Select */
941-
#define DTYPE_NORM 0x0004 /* Data Format Normal */
942-
#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
943-
#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
944-
#define RLSBIT 0x0010 /* Receive Bit Order */
945-
#define IRFS 0x0200 /* Internal Receive Frame Sync Select */
946-
#define RFSR 0x0400 /* Receive Frame Sync Required Select */
947-
#define LRFS 0x1000 /* Low Receive Frame Sync Select */
948-
#define LARFS 0x2000 /* Late Receive Frame Sync Select */
949-
#define RCKFE 0x4000 /* Clock Falling Edge Select */
950-
951-
/* SPORTx_RCR2 Masks */
952-
#define SLEN(x) ((x)&0x1F) /* SPORT RX Word Length (2 - 31) */
953-
#define RXSE 0x0100 /* RX Secondary Enable */
954-
#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */
955-
#define RRFST 0x0400 /* Right-First Data Order */
956-
957-
/* SPORTx_STAT Masks */
958-
#define RXNE 0x0001 /* Receive FIFO Not Empty Status */
959-
#define RUVF 0x0002 /* Sticky Receive Underflow Status */
960-
#define ROVF 0x0004 /* Sticky Receive Overflow Status */
961-
#define TXF 0x0008 /* Transmit FIFO Full Status */
962-
#define TUVF 0x0010 /* Sticky Transmit Underflow Status */
963-
#define TOVF 0x0020 /* Sticky Transmit Overflow Status */
964-
#define TXHRE 0x0040 /* Transmit Hold Register Empty */
965-
966-
/* SPORTx_MCMC1 Macros */
967-
#define SP_WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */
968-
969-
/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits */
970-
#define SP_WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */
971-
972-
/* SPORTx_MCMC2 Masks */
973-
#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
974-
#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
975-
#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
976-
#define MCDTXPE 0x0004 /* Multichannel DMA Transmit Packing */
977-
#define MCDRXPE 0x0008 /* Multichannel DMA Receive Packing */
978-
#define MCMEN 0x0010 /* Multichannel Frame Mode Enable */
979-
#define FSDR 0x0080 /* Multichannel Frame Sync to Data Relationship */
980-
#define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */
981-
#define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */
982-
#define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */
983-
#define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */
984-
#define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */
985-
#define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */
986-
#define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */
987-
#define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */
988-
#define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */
989-
#define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */
990-
#define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */
991-
#define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */
992-
#define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */
993-
#define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */
994-
#define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */
995-
#define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */
996-
997-
998916
/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/
999917
/* EBIU_AMGCTL Masks */
1000918
#define AMCKEN 0x0001 /* Enable CLKOUT */

‎arch/blackfin/mach-bf527/boards/cm_bf527.c

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -145,7 +145,6 @@ static struct mtd_partition partition_info[] = {
145145
};
146146

147147
static struct bf5xx_nand_platform bf5xx_nand_platform = {
148-
.page_size = NFC_PG_SIZE_256,
149148
.data_width = NFC_NWIDTH_8,
150149
.partitions = partition_info,
151150
.nr_partitions = ARRAY_SIZE(partition_info),

‎arch/blackfin/mach-bf527/boards/ezbrd.c

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -149,7 +149,6 @@ static struct mtd_partition partition_info[] = {
149149
};
150150

151151
static struct bf5xx_nand_platform bf5xx_nand_platform = {
152-
.page_size = NFC_PG_SIZE_256,
153152
.data_width = NFC_NWIDTH_8,
154153
.partitions = partition_info,
155154
.nr_partitions = ARRAY_SIZE(partition_info),

‎arch/blackfin/mach-bf527/boards/ezkit.c

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -234,7 +234,6 @@ static struct mtd_partition partition_info[] = {
234234
};
235235

236236
static struct bf5xx_nand_platform bf5xx_nand_platform = {
237-
.page_size = NFC_PG_SIZE_256,
238237
.data_width = NFC_NWIDTH_8,
239238
.partitions = partition_info,
240239
.nr_partitions = ARRAY_SIZE(partition_info),

‎arch/blackfin/mach-bf527/include/mach/defBF52x_base.h

Lines changed: 0 additions & 82 deletions
Original file line numberDiff line numberDiff line change
@@ -922,88 +922,6 @@
922922
#define PH14 0x4000
923923
#define PH15 0x8000
924924

925-
926-
/* ******************* SERIAL PORT MASKS **************************************/
927-
/* SPORTx_TCR1 Masks */
928-
#define TSPEN 0x0001 /* Transmit Enable */
929-
#define ITCLK 0x0002 /* Internal Transmit Clock Select */
930-
#define DTYPE_NORM 0x0004 /* Data Format Normal */
931-
#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
932-
#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
933-
#define TLSBIT 0x0010 /* Transmit Bit Order */
934-
#define ITFS 0x0200 /* Internal Transmit Frame Sync Select */
935-
#define TFSR 0x0400 /* Transmit Frame Sync Required Select */
936-
#define DITFS 0x0800 /* Data-Independent Transmit Frame Sync Select */
937-
#define LTFS 0x1000 /* Low Transmit Frame Sync Select */
938-
#define LATFS 0x2000 /* Late Transmit Frame Sync Select */
939-
#define TCKFE 0x4000 /* Clock Falling Edge Select */
940-
941-
/* SPORTx_TCR2 Masks and Macro */
942-
#define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */
943-
#define TXSE 0x0100 /* TX Secondary Enable */
944-
#define TSFSE 0x0200 /* Transmit Stereo Frame Sync Enable */
945-
#define TRFST 0x0400 /* Left/Right Order (1 = Right Channel 1st) */
946-
947-
/* SPORTx_RCR1 Masks */
948-
#define RSPEN 0x0001 /* Receive Enable */
949-
#define IRCLK 0x0002 /* Internal Receive Clock Select */
950-
#define DTYPE_NORM 0x0004 /* Data Format Normal */
951-
#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
952-
#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
953-
#define RLSBIT 0x0010 /* Receive Bit Order */
954-
#define IRFS 0x0200 /* Internal Receive Frame Sync Select */
955-
#define RFSR 0x0400 /* Receive Frame Sync Required Select */
956-
#define LRFS 0x1000 /* Low Receive Frame Sync Select */
957-
#define LARFS 0x2000 /* Late Receive Frame Sync Select */
958-
#define RCKFE 0x4000 /* Clock Falling Edge Select */
959-
960-
/* SPORTx_RCR2 Masks */
961-
#define SLEN(x) ((x)&0x1F) /* SPORT RX Word Length (2 - 31) */
962-
#define RXSE 0x0100 /* RX Secondary Enable */
963-
#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */
964-
#define RRFST 0x0400 /* Right-First Data Order */
965-
966-
/* SPORTx_STAT Masks */
967-
#define RXNE 0x0001 /* Receive FIFO Not Empty Status */
968-
#define RUVF 0x0002 /* Sticky Receive Underflow Status */
969-
#define ROVF 0x0004 /* Sticky Receive Overflow Status */
970-
#define TXF 0x0008 /* Transmit FIFO Full Status */
971-
#define TUVF 0x0010 /* Sticky Transmit Underflow Status */
972-
#define TOVF 0x0020 /* Sticky Transmit Overflow Status */
973-
#define TXHRE 0x0040 /* Transmit Hold Register Empty */
974-
975-
/* SPORTx_MCMC1 Macros */
976-
#define SP_WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */
977-
978-
/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits */
979-
#define SP_WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */
980-
981-
/* SPORTx_MCMC2 Masks */
982-
#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
983-
#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
984-
#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
985-
#define MCDTXPE 0x0004 /* Multichannel DMA Transmit Packing */
986-
#define MCDRXPE 0x0008 /* Multichannel DMA Receive Packing */
987-
#define MCMEN 0x0010 /* Multichannel Frame Mode Enable */
988-
#define FSDR 0x0080 /* Multichannel Frame Sync to Data Relationship */
989-
#define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */
990-
#define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */
991-
#define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */
992-
#define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */
993-
#define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */
994-
#define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */
995-
#define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */
996-
#define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */
997-
#define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */
998-
#define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */
999-
#define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */
1000-
#define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */
1001-
#define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */
1002-
#define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */
1003-
#define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */
1004-
#define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */
1005-
1006-
1007925
/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/
1008926
/* EBIU_AMGCTL Masks */
1009927
#define AMCKEN 0x0001 /* Enable CLKOUT */

‎arch/blackfin/mach-bf533/include/mach/defBF532.h

Lines changed: 0 additions & 92 deletions
Original file line numberDiff line numberDiff line change
@@ -509,98 +509,6 @@
509509
#define IREN_P 0x01
510510
#define UCEN_P 0x00
511511

512-
/* ********** SERIAL PORT MASKS ********************** */
513-
514-
/* SPORTx_TCR1 Masks */
515-
#define TSPEN 0x0001 /* TX enable */
516-
#define ITCLK 0x0002 /* Internal TX Clock Select */
517-
#define TDTYPE 0x000C /* TX Data Formatting Select */
518-
#define DTYPE_NORM 0x0000 /* Data Format Normal */
519-
#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
520-
#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
521-
#define TLSBIT 0x0010 /* TX Bit Order */
522-
#define ITFS 0x0200 /* Internal TX Frame Sync Select */
523-
#define TFSR 0x0400 /* TX Frame Sync Required Select */
524-
#define DITFS 0x0800 /* Data Independent TX Frame Sync Select */
525-
#define LTFS 0x1000 /* Low TX Frame Sync Select */
526-
#define LATFS 0x2000 /* Late TX Frame Sync Select */
527-
#define TCKFE 0x4000 /* TX Clock Falling Edge Select */
528-
529-
/* SPORTx_TCR2 Masks */
530-
#if defined(__ADSPBF531__) || defined(__ADSPBF532__) || \
531-
defined(__ADSPBF533__)
532-
# define SLEN 0x001F /*TX Word Length */
533-
#else
534-
# define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */
535-
#endif
536-
#define TXSE 0x0100 /*TX Secondary Enable */
537-
#define TSFSE 0x0200 /*TX Stereo Frame Sync Enable */
538-
#define TRFST 0x0400 /*TX Right-First Data Order */
539-
540-
/* SPORTx_RCR1 Masks */
541-
#define RSPEN 0x0001 /* RX enable */
542-
#define IRCLK 0x0002 /* Internal RX Clock Select */
543-
#define RDTYPE 0x000C /* RX Data Formatting Select */
544-
#define DTYPE_NORM 0x0000 /* no companding */
545-
#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
546-
#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
547-
#define RLSBIT 0x0010 /* RX Bit Order */
548-
#define IRFS 0x0200 /* Internal RX Frame Sync Select */
549-
#define RFSR 0x0400 /* RX Frame Sync Required Select */
550-
#define LRFS 0x1000 /* Low RX Frame Sync Select */
551-
#define LARFS 0x2000 /* Late RX Frame Sync Select */
552-
#define RCKFE 0x4000 /* RX Clock Falling Edge Select */
553-
554-
/* SPORTx_RCR2 Masks */
555-
/* SLEN defined above */
556-
#define RXSE 0x0100 /*RX Secondary Enable */
557-
#define RSFSE 0x0200 /*RX Stereo Frame Sync Enable */
558-
#define RRFST 0x0400 /*Right-First Data Order */
559-
560-
/*SPORTx_STAT Masks */
561-
#define RXNE 0x0001 /*RX FIFO Not Empty Status */
562-
#define RUVF 0x0002 /*RX Underflow Status */
563-
#define ROVF 0x0004 /*RX Overflow Status */
564-
#define TXF 0x0008 /*TX FIFO Full Status */
565-
#define TUVF 0x0010 /*TX Underflow Status */
566-
#define TOVF 0x0020 /*TX Overflow Status */
567-
#define TXHRE 0x0040 /*TX Hold Register Empty */
568-
569-
/*SPORTx_MCMC1 Masks */
570-
#define SP_WSIZE 0x0000F000 /*Multichannel Window Size Field */
571-
#define SP_WOFF 0x000003FF /*Multichannel Window Offset Field */
572-
/* SPORTx_MCMC1 Macros */
573-
#define SET_SP_WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */
574-
/* Only use SET_WSIZE Macro With Logic OR While Setting Lower Order Bits */
575-
#define SET_SP_WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */
576-
577-
/*SPORTx_MCMC2 Masks */
578-
#define MCCRM 0x00000003 /*Multichannel Clock Recovery Mode */
579-
#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
580-
#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
581-
#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
582-
#define MCDTXPE 0x00000004 /*Multichannel DMA Transmit Packing */
583-
#define MCDRXPE 0x00000008 /*Multichannel DMA Receive Packing */
584-
#define MCMEN 0x00000010 /*Multichannel Frame Mode Enable */
585-
#define FSDR 0x00000080 /*Multichannel Frame Sync to Data Relationship */
586-
#define MFD 0x0000F000 /*Multichannel Frame Delay */
587-
#define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */
588-
#define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */
589-
#define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */
590-
#define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */
591-
#define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */
592-
#define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */
593-
#define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */
594-
#define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */
595-
#define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */
596-
#define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */
597-
#define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */
598-
#define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */
599-
#define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */
600-
#define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */
601-
#define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */
602-
#define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */
603-
604512
/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */
605513

606514
/* PPI_CONTROL Masks */

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