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Merge tag 'dmaengine-5.1-rc1' of git://git.infradead.org/users/vkoul/slave-dma
Pull dmaengine updates from Vinod Koul: - dmatest updates for modularizing common struct and code - remove SG support for VDMA xilinx IP and updates to driver - Update to dw driver to support Intel iDMA controllers multi-block support - tegra updates for proper reporting of residue - Add Snow Ridge ioatdma device id and support for IOATDMA v3.4 - struct_size() usage and useless LIST_HEAD cleanups in subsystem. - qDMA controller driver for Layerscape SoCs - stm32-dma PM Runtime support - And usual updates to imx-sdma, sprd, Documentation, fsl-edma, bcm2835, qcom_hidma etc * tag 'dmaengine-5.1-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (81 commits) dmaengine: imx-sdma: fix consistent dma test failures dmaengine: imx-sdma: add a test for imx8mq multi sdma devices dmaengine: imx-sdma: add clock ratio 1:1 check dmaengine: dmatest: move test data alloc & free into functions dmaengine: dmatest: add short-hand `buf_size` var in dmatest_func() dmaengine: dmatest: wrap src & dst data into a struct dmaengine: ioatdma: support latency tolerance report (LTR) for v3.4 dmaengine: ioatdma: add descriptor pre-fetch support for v3.4 dmaengine: ioatdma: disable DCA enabling on IOATDMA v3.4 dmaengine: ioatdma: Add Snow Ridge ioatdma device id dmaengine: sprd: Change channel id to slave id for DMA cell specifier dt-bindings: dmaengine: sprd: Change channel id to slave id for DMA cell specifier dmaengine: mv_xor: Use correct device for DMA API Documentation :dmaengine: clarify DMA desc. pointer after submission Documentation: dmaengine: fix dmatest.rst warning dmaengine: k3dma: Add support for dma-channel-mask dmaengine: k3dma: Delete axi_config dmaengine: k3dma: Upgrade k3dma driver to support hisi_asp_dma hardware Documentation: bindings: dma: Add binding for dma-channel-mask Documentation: bindings: k3dma: Extend the k3dma driver binding to support hisi-asp ...
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‎Documentation/devicetree/bindings/dma/dma.txt

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,9 @@ Optional properties:
1616
- dma-channels: Number of DMA channels supported by the controller.
1717
- dma-requests: Number of DMA request signals supported by the
1818
controller.
19+
- dma-channel-mask: Bitmask of available DMA channels in ascending order
20+
that are not reserved by firmware and are available to
21+
the kernel. i.e. first channel corresponds to LSB.
1922

2023
Example:
2124

@@ -29,6 +32,7 @@ Example:
2932
#dma-cells = <1>;
3033
dma-channels = <32>;
3134
dma-requests = <127>;
35+
dma-channel-mask = <0xfffe>
3236
};
3337

3438
* DMA router

‎Documentation/devicetree/bindings/dma/fsl-qdma.txt

Lines changed: 57 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,57 @@
1+
NXP Layerscape SoC qDMA Controller
2+
==================================
3+
4+
This device follows the generic DMA bindings defined in dma/dma.txt.
5+
6+
Required properties:
7+
8+
- compatible: Must be one of
9+
"fsl,ls1021a-qdma": for LS1021A Board
10+
"fsl,ls1043a-qdma": for ls1043A Board
11+
"fsl,ls1046a-qdma": for ls1046A Board
12+
- reg: Should contain the register's base address and length.
13+
- interrupts: Should contain a reference to the interrupt used by this
14+
device.
15+
- interrupt-names: Should contain interrupt names:
16+
"qdma-queue0": the block0 interrupt
17+
"qdma-queue1": the block1 interrupt
18+
"qdma-queue2": the block2 interrupt
19+
"qdma-queue3": the block3 interrupt
20+
"qdma-error": the error interrupt
21+
- fsl,dma-queues: Should contain number of queues supported.
22+
- dma-channels: Number of DMA channels supported
23+
- block-number: the virtual block number
24+
- block-offset: the offset of different virtual block
25+
- status-sizes: status queue size of per virtual block
26+
- queue-sizes: command queue size of per virtual block, the size number
27+
based on queues
28+
29+
Optional properties:
30+
31+
- dma-channels: Number of DMA channels supported by the controller.
32+
- big-endian: If present registers and hardware scatter/gather descriptors
33+
of the qDMA are implemented in big endian mode, otherwise in little
34+
mode.
35+
36+
Examples:
37+
38+
qdma: dma-controller@8390000 {
39+
compatible = "fsl,ls1021a-qdma";
40+
reg = <0x0 0x8388000 0x0 0x1000>, /* Controller regs */
41+
<0x0 0x8389000 0x0 0x1000>, /* Status regs */
42+
<0x0 0x838a000 0x0 0x2000>; /* Block regs */
43+
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
44+
<GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
45+
<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
46+
interrupt-names = "qdma-error",
47+
"qdma-queue0", "qdma-queue1";
48+
dma-channels = <8>;
49+
block-number = <2>;
50+
block-offset = <0x1000>;
51+
fsl,dma-queues = <2>;
52+
status-sizes = <64>;
53+
queue-sizes = <64 64>;
54+
big-endian;
55+
};
56+
57+
DMA clients must use the format described in dma/dma.txt file.

‎Documentation/devicetree/bindings/dma/k3dma.txt

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,9 @@
33
See dma.txt first
44

55
Required properties:
6-
- compatible: Should be "hisilicon,k3-dma-1.0"
6+
- compatible: Must be one of
7+
- "hisilicon,k3-dma-1.0"
8+
- "hisilicon,hisi-pcm-asp-dma-1.0"
79
- reg: Should contain DMA registers location and length.
810
- interrupts: Should contain one interrupt shared by all channel
911
- #dma-cells: see dma.txt, should be 1, para number

‎Documentation/devicetree/bindings/dma/snps-dma.txt

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Original file line numberDiff line numberDiff line change
@@ -23,8 +23,6 @@ Deprecated properties:
2323

2424

2525
Optional properties:
26-
- is_private: The device channels should be marked as private and not for by the
27-
general purpose DMA channel allocator. False if not passed.
2826
- multi-block: Multi block transfers supported by hardware. Array property with
2927
one cell per channel. 0: not supported, 1 (default): supported.
3028
- snps,dma-protection-control: AHB HPROT[3:1] protection setting.

‎Documentation/devicetree/bindings/dma/sprd-dma.txt

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Original file line numberDiff line numberDiff line change
@@ -31,7 +31,7 @@ DMA clients connected to the Spreadtrum DMA controller must use the format
3131
described in the dma.txt file, using a two-cell specifier for each channel.
3232
The two cells in order are:
3333
1. A phandle pointing to the DMA controller.
34-
2. The channel id.
34+
2. The slave id.
3535

3636
spi0: spi@70a00000{
3737
...

‎Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt

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Original file line numberDiff line numberDiff line change
@@ -37,10 +37,11 @@ Required properties:
3737
Required properties for VDMA:
3838
- xlnx,num-fstores: Should be the number of framebuffers as configured in h/w.
3939

40-
Optional properties:
41-
- xlnx,include-sg: Tells configured for Scatter-mode in
42-
the hardware.
4340
Optional properties for AXI DMA:
41+
- xlnx,sg-length-width: Should be set to the width in bits of the length
42+
register as configured in h/w. Takes values {8...26}. If the property
43+
is missing or invalid then the default value 23 is used. This is the
44+
maximum value that is supported by all IP versions.
4445
- xlnx,mcdma: Tells whether configured for multi-channel mode in the hardware.
4546
Optional properties for VDMA:
4647
- xlnx,flush-fsync: Tells which channel to Flush on Frame sync.

‎Documentation/driver-api/dmaengine/client.rst

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@@ -172,7 +172,7 @@ The details of these operations are:
172172

173173
After calling ``dmaengine_submit()`` the submitted transfer descriptor
174174
(``struct dma_async_tx_descriptor``) belongs to the DMA engine.
175-
Consequentially, the client must consider invalid the pointer to that
175+
Consequently, the client must consider invalid the pointer to that
176176
descriptor.
177177

178178
5. Issue pending DMA requests and wait for callback notification

‎Documentation/driver-api/dmaengine/dmatest.rst

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Original file line numberDiff line numberDiff line change
@@ -59,6 +59,7 @@ parameter, that specific channel is requested using the dmaengine and a thread
5959
is created with the existing parameters. This thread is set as pending
6060
and will be executed once run is set to 1. Any parameters set after the thread
6161
is created are not applied.
62+
6263
.. hint::
6364
available channel list could be extracted by running the following command::
6465

‎drivers/dma/Kconfig

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@@ -218,6 +218,20 @@ config FSL_EDMA
218218
multiplexing capability for DMA request sources(slot).
219219
This module can be found on Freescale Vybrid and LS-1 SoCs.
220220

221+
config FSL_QDMA
222+
tristate "NXP Layerscape qDMA engine support"
223+
depends on ARM || ARM64
224+
select DMA_ENGINE
225+
select DMA_VIRTUAL_CHANNELS
226+
select DMA_ENGINE_RAID
227+
select ASYNC_TX_ENABLE_CHANNEL_SWITCH
228+
help
229+
Support the NXP Layerscape qDMA engine with command queue and legacy mode.
230+
Channel virtualization is supported through enqueuing of DMA jobs to,
231+
or dequeuing DMA jobs from, different work queues.
232+
This module can be found on NXP Layerscape SoCs.
233+
The qdma driver only work on SoCs with a DPAA hardware block.
234+
221235
config FSL_RAID
222236
tristate "Freescale RAID engine Support"
223237
depends on FSL_SOC && !ASYNC_TX_ENABLE_CHANNEL_SWITCH

‎drivers/dma/Makefile

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Original file line numberDiff line numberDiff line change
@@ -33,6 +33,7 @@ obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o
3333
obj-$(CONFIG_FSL_DMA) += fsldma.o
3434
obj-$(CONFIG_FSL_EDMA) += fsl-edma.o fsl-edma-common.o
3535
obj-$(CONFIG_MCF_EDMA) += mcf-edma.o fsl-edma-common.o
36+
obj-$(CONFIG_FSL_QDMA) += fsl-qdma.o
3637
obj-$(CONFIG_FSL_RAID) += fsl_raid.o
3738
obj-$(CONFIG_HSU_DMA) += hsu/
3839
obj-$(CONFIG_IMG_MDC_DMA) += img-mdc-dma.o

‎drivers/dma/at_hdmac.c

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Original file line numberDiff line numberDiff line change
@@ -134,7 +134,6 @@ static struct at_desc *atc_desc_get(struct at_dma_chan *atchan)
134134
struct at_desc *ret = NULL;
135135
unsigned long flags;
136136
unsigned int i = 0;
137-
LIST_HEAD(tmp_list);
138137

139138
spin_lock_irqsave(&atchan->lock, flags);
140139
list_for_each_entry_safe(desc, _desc, &atchan->free_list, desc_node) {
@@ -1387,8 +1386,6 @@ static int atc_pause(struct dma_chan *chan)
13871386
int chan_id = atchan->chan_common.chan_id;
13881387
unsigned long flags;
13891388

1390-
LIST_HEAD(list);
1391-
13921389
dev_vdbg(chan2dev(chan), "%s\n", __func__);
13931390

13941391
spin_lock_irqsave(&atchan->lock, flags);
@@ -1408,8 +1405,6 @@ static int atc_resume(struct dma_chan *chan)
14081405
int chan_id = atchan->chan_common.chan_id;
14091406
unsigned long flags;
14101407

1411-
LIST_HEAD(list);
1412-
14131408
dev_vdbg(chan2dev(chan), "%s\n", __func__);
14141409

14151410
if (!atc_chan_is_paused(atchan))

‎drivers/dma/bcm2835-dma.c

Lines changed: 8 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -2,9 +2,6 @@
22
/*
33
* BCM2835 DMA engine support
44
*
5-
* This driver only supports cyclic DMA transfers
6-
* as needed for the I2S module.
7-
*
85
* Author: Florian Meier <florian.meier@koalo.de>
96
* Copyright 2013
107
*
@@ -42,7 +39,6 @@
4239

4340
struct bcm2835_dmadev {
4441
struct dma_device ddev;
45-
spinlock_t lock;
4642
void __iomem *base;
4743
struct device_dma_parameters dma_parms;
4844
};
@@ -64,7 +60,6 @@ struct bcm2835_cb_entry {
6460

6561
struct bcm2835_chan {
6662
struct virt_dma_chan vc;
67-
struct list_head node;
6863

6964
struct dma_slave_config cfg;
7065
unsigned int dreq;
@@ -312,8 +307,7 @@ static struct bcm2835_desc *bcm2835_dma_create_cb_chain(
312307
return NULL;
313308

314309
/* allocate and setup the descriptor. */
315-
d = kzalloc(sizeof(*d) + frames * sizeof(struct bcm2835_cb_entry),
316-
gfp);
310+
d = kzalloc(struct_size(d, cb_list, frames), gfp);
317311
if (!d)
318312
return NULL;
319313

@@ -406,7 +400,7 @@ static void bcm2835_dma_fill_cb_chain_with_sg(
406400
}
407401
}
408402

409-
static int bcm2835_dma_abort(struct bcm2835_chan *c)
403+
static void bcm2835_dma_abort(struct bcm2835_chan *c)
410404
{
411405
void __iomem *chan_base = c->chan_base;
412406
long int timeout = 10000;
@@ -416,7 +410,7 @@ static int bcm2835_dma_abort(struct bcm2835_chan *c)
416410
* (The ACTIVE flag in the CS register is not a reliable indicator.)
417411
*/
418412
if (!readl(chan_base + BCM2835_DMA_ADDR))
419-
return 0;
413+
return;
420414

421415
/* Write 0 to the active bit - Pause the DMA */
422416
writel(0, chan_base + BCM2835_DMA_CS);
@@ -432,7 +426,6 @@ static int bcm2835_dma_abort(struct bcm2835_chan *c)
432426
"failed to complete outstanding writes\n");
433427

434428
writel(BCM2835_DMA_RESET, chan_base + BCM2835_DMA_CS);
435-
return 0;
436429
}
437430

438431
static void bcm2835_dma_start_desc(struct bcm2835_chan *c)
@@ -504,8 +497,12 @@ static int bcm2835_dma_alloc_chan_resources(struct dma_chan *chan)
504497

505498
dev_dbg(dev, "Allocating DMA channel %d\n", c->ch);
506499

500+
/*
501+
* Control blocks are 256 bit in length and must start at a 256 bit
502+
* (32 byte) aligned address (BCM2835 ARM Peripherals, sec. 4.2.1.1).
503+
*/
507504
c->cb_pool = dma_pool_create(dev_name(dev), dev,
508-
sizeof(struct bcm2835_dma_cb), 0, 0);
505+
sizeof(struct bcm2835_dma_cb), 32, 0);
509506
if (!c->cb_pool) {
510507
dev_err(dev, "unable to allocate descriptor pool\n");
511508
return -ENOMEM;
@@ -774,17 +771,11 @@ static int bcm2835_dma_slave_config(struct dma_chan *chan,
774771
static int bcm2835_dma_terminate_all(struct dma_chan *chan)
775772
{
776773
struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
777-
struct bcm2835_dmadev *d = to_bcm2835_dma_dev(c->vc.chan.device);
778774
unsigned long flags;
779775
LIST_HEAD(head);
780776

781777
spin_lock_irqsave(&c->vc.lock, flags);
782778

783-
/* Prevent this channel being scheduled */
784-
spin_lock(&d->lock);
785-
list_del_init(&c->node);
786-
spin_unlock(&d->lock);
787-
788779
/* stop DMA activity */
789780
if (c->desc) {
790781
vchan_terminate_vdesc(&c->desc->vd);
@@ -817,7 +808,6 @@ static int bcm2835_dma_chan_init(struct bcm2835_dmadev *d, int chan_id,
817808

818809
c->vc.desc_free = bcm2835_dma_desc_free;
819810
vchan_init(&c->vc, &d->ddev);
820-
INIT_LIST_HEAD(&c->node);
821811

822812
c->chan_base = BCM2835_DMA_CHANIO(d->base, chan_id);
823813
c->ch = chan_id;
@@ -920,7 +910,6 @@ static int bcm2835_dma_probe(struct platform_device *pdev)
920910
od->ddev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
921911
od->ddev.dev = &pdev->dev;
922912
INIT_LIST_HEAD(&od->ddev.channels);
923-
spin_lock_init(&od->lock);
924913

925914
platform_set_drvdata(pdev, od);
926915

‎drivers/dma/dma-axi-dmac.c

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -367,8 +367,7 @@ static struct axi_dmac_desc *axi_dmac_alloc_desc(unsigned int num_sgs)
367367
struct axi_dmac_desc *desc;
368368
unsigned int i;
369369

370-
desc = kzalloc(sizeof(struct axi_dmac_desc) +
371-
sizeof(struct axi_dmac_sg) * num_sgs, GFP_NOWAIT);
370+
desc = kzalloc(struct_size(desc, sg, num_sgs), GFP_NOWAIT);
372371
if (!desc)
373372
return NULL;
374373

‎drivers/dma/dma-jz4780.c

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -838,9 +838,8 @@ static int jz4780_dma_probe(struct platform_device *pdev)
838838
if (!soc_data)
839839
return -EINVAL;
840840

841-
jzdma = devm_kzalloc(dev, sizeof(*jzdma)
842-
+ sizeof(*jzdma->chan) * soc_data->nb_channels,
843-
GFP_KERNEL);
841+
jzdma = devm_kzalloc(dev, struct_size(jzdma, chan,
842+
soc_data->nb_channels), GFP_KERNEL);
844843
if (!jzdma)
845844
return -ENOMEM;
846845

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