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Merge branch 'mlx5-DCBX-and-ethtool-updates'
Saeed Mahameed says: ==================== Mellanox 100G mlx5 DCBX and ethtool updates This series provides the following mlx5 updates: From Huy: DCBX CEE API and DCBX firmware/host modes support. - 1st patch ensures the dcbnl_rtnl_ops is published only when the qos capability bits is on. - 2nd patch adds the support for CEE interfaces into mlx5 dcbnl_rtnl_ops - 3rd patch refactors ETS query to read ETS configuration directly from firmware rather than having a software shadow to it. The existing IEEE interfaces stays the same. - 4th patch adds the support for MLX5_REG_DCBX_PARAM and MLX5_REG_DCBX_APP firmware commands to manipulate mlx5 DCBX mode. - 5th patch adds the driver support for the new DCBX firmware. This ensures the backward compatibility versus the old and new firmware. With the new DCBX firmware, qos settings can be controlled by either firmware or software depending on the DCBX mode. From Kamal and Saeed: - mlx5 self-test support. From Shaker: - Private flag to give the user the ability to enable/disable mlx5 CQE compression. V1->V2: - Check ETS capability where needed in: ("net/mlx5e: Read ETS settings directly from firmware") - Fix return value of mlx5e_dcbnl_switch_to_host_mode in: ("net/mlx5e: ConnectX-4 firmware support for DCBX") - Update commit message of: ("net/mlx5e: ConnectX-4 firmware support for DCBX") - Fix two sparse static check warnings in en_selftest.c This series was generated against commit: e5f12b3 ("Merge branch 'mlxsw-trap-groups-and-policers'") ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
2 parents 4490001 + 9bcc860 commit 33362fc

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lines changed

‎drivers/net/ethernet/mellanox/mlx5/core/Makefile

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,6 @@ mlx5_core-y := main.o cmd.o debugfs.o fw.o eq.o uar.o pagealloc.o \
88
mlx5_core-$(CONFIG_MLX5_CORE_EN) += wq.o eswitch.o eswitch_offloads.o \
99
en_main.o en_common.o en_fs.o en_ethtool.o en_tx.o \
1010
en_rx.o en_rx_am.o en_txrx.o en_clock.o vxlan.o \
11-
en_tc.o en_arfs.o en_rep.o en_fs_ethtool.o
11+
en_tc.o en_arfs.o en_rep.o en_fs_ethtool.o en_selftest.o
1212

1313
mlx5_core-$(CONFIG_MLX5_CORE_EN_DCB) += en_dcbnl.o

‎drivers/net/ethernet/mellanox/mlx5/core/en.h

Lines changed: 48 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -167,22 +167,28 @@ struct mlx5e_umr_wqe {
167167
struct mlx5_wqe_data_seg data;
168168
};
169169

170+
extern const char mlx5e_self_tests[][ETH_GSTRING_LEN];
171+
170172
static const char mlx5e_priv_flags[][ETH_GSTRING_LEN] = {
171173
"rx_cqe_moder",
174+
"rx_cqe_compress",
172175
};
173176

174177
enum mlx5e_priv_flag {
175178
MLX5E_PFLAG_RX_CQE_BASED_MODER = (1 << 0),
179+
MLX5E_PFLAG_RX_CQE_COMPRESS = (1 << 1),
176180
};
177181

178-
#define MLX5E_SET_PRIV_FLAG(priv, pflag, enable) \
179-
do { \
180-
if (enable) \
181-
priv->pflags |= pflag; \
182-
else \
183-
priv->pflags &= ~pflag; \
182+
#define MLX5E_SET_PFLAG(priv, pflag, enable) \
183+
do { \
184+
if (enable) \
185+
(priv)->params.pflags |= (pflag); \
186+
else \
187+
(priv)->params.pflags &= ~(pflag); \
184188
} while (0)
185189

190+
#define MLX5E_GET_PFLAG(priv, pflag) (!!((priv)->params.pflags & (pflag)))
191+
186192
#ifdef CONFIG_MLX5_CORE_EN_DCB
187193
#define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */
188194
#endif
@@ -201,8 +207,7 @@ struct mlx5e_params {
201207
u16 num_channels;
202208
u8 num_tc;
203209
u8 rx_cq_period_mode;
204-
bool rx_cqe_compress_admin;
205-
bool rx_cqe_compress;
210+
bool rx_cqe_compress_def;
206211
struct mlx5e_cq_moder rx_cq_moderation;
207212
struct mlx5e_cq_moder tx_cq_moderation;
208213
u16 min_rx_wqes;
@@ -214,13 +219,35 @@ struct mlx5e_params {
214219
u8 toeplitz_hash_key[40];
215220
u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE];
216221
bool vlan_strip_disable;
217-
#ifdef CONFIG_MLX5_CORE_EN_DCB
218-
struct ieee_ets ets;
219-
#endif
220222
bool rx_am_enabled;
221223
u32 lro_timeout;
224+
u32 pflags;
222225
};
223226

227+
#ifdef CONFIG_MLX5_CORE_EN_DCB
228+
struct mlx5e_cee_config {
229+
/* bw pct for priority group */
230+
u8 pg_bw_pct[CEE_DCBX_MAX_PGS];
231+
u8 prio_to_pg_map[CEE_DCBX_MAX_PRIO];
232+
bool pfc_setting[CEE_DCBX_MAX_PRIO];
233+
bool pfc_enable;
234+
};
235+
236+
enum {
237+
MLX5_DCB_CHG_RESET,
238+
MLX5_DCB_NO_CHG,
239+
MLX5_DCB_CHG_NO_RESET,
240+
};
241+
242+
struct mlx5e_dcbx {
243+
enum mlx5_dcbx_oper_mode mode;
244+
struct mlx5e_cee_config cee_cfg; /* pending configuration */
245+
246+
/* The only setting that cannot be read from FW */
247+
u8 tc_tsa[IEEE_8021QAZ_MAX_TCS];
248+
};
249+
#endif
250+
224251
struct mlx5e_tstamp {
225252
rwlock_t lock;
226253
struct cyclecounter cycles;
@@ -682,12 +709,15 @@ struct mlx5e_priv {
682709
struct work_struct tx_timeout_work;
683710
struct delayed_work update_stats_work;
684711

685-
u32 pflags;
686712
struct mlx5_core_dev *mdev;
687713
struct net_device *netdev;
688714
struct mlx5e_stats stats;
689715
struct mlx5e_tstamp tstamp;
690716
u16 q_counter;
717+
#ifdef CONFIG_MLX5_CORE_EN_DCB
718+
struct mlx5e_dcbx dcbx;
719+
#endif
720+
691721
const struct mlx5e_profile *profile;
692722
void *ppriv;
693723
};
@@ -729,6 +759,9 @@ int mlx5e_create_flow_steering(struct mlx5e_priv *priv);
729759
void mlx5e_destroy_flow_steering(struct mlx5e_priv *priv);
730760
void mlx5e_init_l2_addr(struct mlx5e_priv *priv);
731761
void mlx5e_destroy_flow_table(struct mlx5e_flow_table *ft);
762+
int mlx5e_self_test_num(struct mlx5e_priv *priv);
763+
void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest,
764+
u64 *buf);
732765
int mlx5e_ethtool_get_flow(struct mlx5e_priv *priv, struct ethtool_rxnfc *info,
733766
int location);
734767
int mlx5e_ethtool_get_all_flows(struct mlx5e_priv *priv,
@@ -819,6 +852,7 @@ extern const struct ethtool_ops mlx5e_ethtool_ops;
819852
#ifdef CONFIG_MLX5_CORE_EN_DCB
820853
extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops;
821854
int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets);
855+
void mlx5e_dcbnl_initialize(struct mlx5e_priv *priv);
822856
#endif
823857

824858
#ifndef CONFIG_RFS_ACCEL
@@ -854,7 +888,8 @@ void mlx5e_destroy_tir(struct mlx5_core_dev *mdev,
854888
struct mlx5e_tir *tir);
855889
int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev);
856890
void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev);
857-
int mlx5e_refresh_tirs_self_loopback_enable(struct mlx5_core_dev *mdev);
891+
int mlx5e_refresh_tirs_self_loopback(struct mlx5_core_dev *mdev,
892+
bool enable_uc_lb);
858893

859894
struct mlx5_eswitch_rep;
860895
int mlx5e_vport_rep_load(struct mlx5_eswitch *esw,

‎drivers/net/ethernet/mellanox/mlx5/core/en_clock.c

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -94,7 +94,7 @@ int mlx5e_hwstamp_set(struct net_device *dev, struct ifreq *ifr)
9494
switch (config.rx_filter) {
9595
case HWTSTAMP_FILTER_NONE:
9696
/* Reset CQE compression to Admin default */
97-
mlx5e_modify_rx_cqe_compression(priv, priv->params.rx_cqe_compress_admin);
97+
mlx5e_modify_rx_cqe_compression(priv, priv->params.rx_cqe_compress_def);
9898
break;
9999
case HWTSTAMP_FILTER_ALL:
100100
case HWTSTAMP_FILTER_SOME:
@@ -111,6 +111,7 @@ int mlx5e_hwstamp_set(struct net_device *dev, struct ifreq *ifr)
111111
case HWTSTAMP_FILTER_PTP_V2_SYNC:
112112
case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
113113
/* Disable CQE compression */
114+
netdev_warn(dev, "Disabling cqe compression");
114115
mlx5e_modify_rx_cqe_compression(priv, false);
115116
config.rx_filter = HWTSTAMP_FILTER_ALL;
116117
break;

‎drivers/net/ethernet/mellanox/mlx5/core/en_common.c

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -137,7 +137,8 @@ void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev)
137137
mlx5_unmap_free_uar(mdev, &res->cq_uar);
138138
}
139139

140-
int mlx5e_refresh_tirs_self_loopback_enable(struct mlx5_core_dev *mdev)
140+
int mlx5e_refresh_tirs_self_loopback(struct mlx5_core_dev *mdev,
141+
bool enable_uc_lb)
141142
{
142143
struct mlx5e_tir *tir;
143144
void *in;
@@ -149,6 +150,10 @@ int mlx5e_refresh_tirs_self_loopback_enable(struct mlx5_core_dev *mdev)
149150
if (!in)
150151
return -ENOMEM;
151152

153+
if (enable_uc_lb)
154+
MLX5_SET(modify_tir_in, in, ctx.self_lb_block,
155+
MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_);
156+
152157
MLX5_SET(modify_tir_in, in, bitmask.self_lb_en, 1);
153158

154159
list_for_each_entry(tir, &mdev->mlx5e_res.td.tirs_list, list) {

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