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Merge branch 'drm-next-4.17' of git://people.freedesktop.org/~agd5f/linux into drm-next
Last pull for 4.17. Highlights: - Vega12 support - A few more bug fixes and cleanups for powerplay * 'drm-next-4.17' of git://people.freedesktop.org/~agd5f/linux: (77 commits) drm/amd/pp: clean header file hwmgr.h drm/amd/pp: use mlck_table.count for array loop index limit drm/amdgpu: Add an ATPX quirk for hybrid laptop drm/amdgpu: fix spelling mistake: "asssert" -> "assert" drm/amd/pp: Add new asic support in pp_psm.c drm/amd/pp: Clean up powerplay code on Vega12 drm/amd/pp: Add smu irq handlers for legacy asics drm/amd/pp: Fix set wrong temperature range on smu7 drm/amdgpu: Don't change preferred domian when fallback GTT v5 drm/amdgpu: Fix NULL ptr on driver unload due to init failure. drm/amdgpu: fix "mitigate workaround for i915" drm/amd/pp: Add smu irq handlers in sw_init instand of hw_init drm/amd/pp: Refine register_thermal_interrupt function drm/amdgpu: Remove wrapper layer of cgs irq handling drm/amd/powerplay: Return per DPM level clock drm/amd/powerplay: Remove the SOC floor voltage setting drm/amdgpu: no job timeout setting on compute queues drm/amdgpu: add vega12 pci ids (v2) drm/amd/powerplay: add the hw manager for vega12 (v4) drm/amd/powerplay: add the smu manager for vega12 (v4) ...
2 parents b4eec0f + 09695ad commit 33d009c

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lines changed

‎drivers/gpu/drm/amd/acp/include/acp_gfx_if.h

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -25,7 +25,6 @@
2525
#define _ACP_GFX_IF_H
2626

2727
#include <linux/types.h>
28-
#include "cgs_linux.h"
2928
#include "cgs_common.h"
3029

3130
int amd_acp_hw_init(struct cgs_device *cgs_device,

‎drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -569,6 +569,7 @@ static const struct amdgpu_px_quirk amdgpu_px_quirk_list[] = {
569569
{ 0x1002, 0x6900, 0x1002, 0x0124, AMDGPU_PX_QUIRK_FORCE_ATPX },
570570
{ 0x1002, 0x6900, 0x1028, 0x0812, AMDGPU_PX_QUIRK_FORCE_ATPX },
571571
{ 0x1002, 0x6900, 0x1028, 0x0813, AMDGPU_PX_QUIRK_FORCE_ATPX },
572+
{ 0x1002, 0x67DF, 0x1028, 0x0774, AMDGPU_PX_QUIRK_FORCE_ATPX },
572573
{ 0, 0, 0, 0, 0 },
573574
};
574575

‎drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c

Lines changed: 4 additions & 115 deletions
Original file line numberDiff line numberDiff line change
@@ -28,7 +28,6 @@
2828
#include <linux/firmware.h>
2929
#include <drm/amdgpu_drm.h>
3030
#include "amdgpu.h"
31-
#include "cgs_linux.h"
3231
#include "atom.h"
3332
#include "amdgpu_ucode.h"
3433

@@ -182,109 +181,6 @@ static int amdgpu_cgs_atom_exec_cmd_table(struct cgs_device *cgs_device, unsigne
182181
adev->mode_info.atom_context, table, args);
183182
}
184183

185-
struct cgs_irq_params {
186-
unsigned src_id;
187-
cgs_irq_source_set_func_t set;
188-
cgs_irq_handler_func_t handler;
189-
void *private_data;
190-
};
191-
192-
static int cgs_set_irq_state(struct amdgpu_device *adev,
193-
struct amdgpu_irq_src *src,
194-
unsigned type,
195-
enum amdgpu_interrupt_state state)
196-
{
197-
struct cgs_irq_params *irq_params =
198-
(struct cgs_irq_params *)src->data;
199-
if (!irq_params)
200-
return -EINVAL;
201-
if (!irq_params->set)
202-
return -EINVAL;
203-
return irq_params->set(irq_params->private_data,
204-
irq_params->src_id,
205-
type,
206-
(int)state);
207-
}
208-
209-
static int cgs_process_irq(struct amdgpu_device *adev,
210-
struct amdgpu_irq_src *source,
211-
struct amdgpu_iv_entry *entry)
212-
{
213-
struct cgs_irq_params *irq_params =
214-
(struct cgs_irq_params *)source->data;
215-
if (!irq_params)
216-
return -EINVAL;
217-
if (!irq_params->handler)
218-
return -EINVAL;
219-
return irq_params->handler(irq_params->private_data,
220-
irq_params->src_id,
221-
entry->iv_entry);
222-
}
223-
224-
static const struct amdgpu_irq_src_funcs cgs_irq_funcs = {
225-
.set = cgs_set_irq_state,
226-
.process = cgs_process_irq,
227-
};
228-
229-
static int amdgpu_cgs_add_irq_source(void *cgs_device,
230-
unsigned client_id,
231-
unsigned src_id,
232-
unsigned num_types,
233-
cgs_irq_source_set_func_t set,
234-
cgs_irq_handler_func_t handler,
235-
void *private_data)
236-
{
237-
CGS_FUNC_ADEV;
238-
int ret = 0;
239-
struct cgs_irq_params *irq_params;
240-
struct amdgpu_irq_src *source =
241-
kzalloc(sizeof(struct amdgpu_irq_src), GFP_KERNEL);
242-
if (!source)
243-
return -ENOMEM;
244-
irq_params =
245-
kzalloc(sizeof(struct cgs_irq_params), GFP_KERNEL);
246-
if (!irq_params) {
247-
kfree(source);
248-
return -ENOMEM;
249-
}
250-
source->num_types = num_types;
251-
source->funcs = &cgs_irq_funcs;
252-
irq_params->src_id = src_id;
253-
irq_params->set = set;
254-
irq_params->handler = handler;
255-
irq_params->private_data = private_data;
256-
source->data = (void *)irq_params;
257-
ret = amdgpu_irq_add_id(adev, client_id, src_id, source);
258-
if (ret) {
259-
kfree(irq_params);
260-
kfree(source);
261-
}
262-
263-
return ret;
264-
}
265-
266-
static int amdgpu_cgs_irq_get(void *cgs_device, unsigned client_id,
267-
unsigned src_id, unsigned type)
268-
{
269-
CGS_FUNC_ADEV;
270-
271-
if (!adev->irq.client[client_id].sources)
272-
return -EINVAL;
273-
274-
return amdgpu_irq_get(adev, adev->irq.client[client_id].sources[src_id], type);
275-
}
276-
277-
static int amdgpu_cgs_irq_put(void *cgs_device, unsigned client_id,
278-
unsigned src_id, unsigned type)
279-
{
280-
CGS_FUNC_ADEV;
281-
282-
if (!adev->irq.client[client_id].sources)
283-
return -EINVAL;
284-
285-
return amdgpu_irq_put(adev, adev->irq.client[client_id].sources[src_id], type);
286-
}
287-
288184
static int amdgpu_cgs_set_clockgating_state(struct cgs_device *cgs_device,
289185
enum amd_ip_block_type block_type,
290186
enum amd_clockgating_state state)
@@ -654,6 +550,9 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,
654550
else
655551
strcpy(fw_name, "amdgpu/vega10_smc.bin");
656552
break;
553+
case CHIP_VEGA12:
554+
strcpy(fw_name, "amdgpu/vega12_smc.bin");
555+
break;
657556
default:
658557
DRM_ERROR("SMC firmware not supported\n");
659558
return -EINVAL;
@@ -715,12 +614,9 @@ static int amdgpu_cgs_get_active_displays_info(struct cgs_device *cgs_device,
715614
return -EINVAL;
716615

717616
mode_info = info->mode_info;
718-
if (mode_info) {
617+
if (mode_info)
719618
/* if the displays are off, vblank time is max */
720619
mode_info->vblank_time_us = 0xffffffff;
721-
/* always set the reference clock */
722-
mode_info->ref_clock = adev->clock.spll.reference_freq;
723-
}
724620

725621
if (!amdgpu_device_has_dc_support(adev)) {
726622
struct amdgpu_crtc *amdgpu_crtc;
@@ -795,12 +691,6 @@ static const struct cgs_ops amdgpu_cgs_ops = {
795691
.lock_grbm_idx = amdgpu_cgs_lock_grbm_idx,
796692
};
797693

798-
static const struct cgs_os_ops amdgpu_cgs_os_ops = {
799-
.add_irq_source = amdgpu_cgs_add_irq_source,
800-
.irq_get = amdgpu_cgs_irq_get,
801-
.irq_put = amdgpu_cgs_irq_put
802-
};
803-
804694
struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev)
805695
{
806696
struct amdgpu_cgs_device *cgs_device =
@@ -812,7 +702,6 @@ struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev)
812702
}
813703

814704
cgs_device->base.ops = &amdgpu_cgs_ops;
815-
cgs_device->base.os_ops = &amdgpu_cgs_os_ops;
816705
cgs_device->adev = adev;
817706

818707
return (struct cgs_device *)cgs_device;

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