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robherringbjorn-helgaas
robherring
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PCI: xgene: Convert to use generic config accessors
Convert the xgene host PCI driver to use the generic config access functions. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: Tanmay Inamdar <tinamdar@apm.com> CC: linux-arm-kernel@lists.infradead.org
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‎drivers/pci/host/pci-xgene.c

Lines changed: 9 additions & 141 deletions
Original file line numberDiff line numberDiff line change
@@ -74,92 +74,6 @@ static inline u32 pcie_bar_low_val(u32 addr, u32 flags)
7474
return (addr & PCI_BASE_ADDRESS_MEM_MASK) | flags;
7575
}
7676

77-
/* PCIe Configuration Out/In */
78-
static inline void xgene_pcie_cfg_out32(void __iomem *addr, int offset, u32 val)
79-
{
80-
writel(val, addr + offset);
81-
}
82-
83-
static inline void xgene_pcie_cfg_out16(void __iomem *addr, int offset, u16 val)
84-
{
85-
u32 val32 = readl(addr + (offset & ~0x3));
86-
87-
switch (offset & 0x3) {
88-
case 2:
89-
val32 &= ~0xFFFF0000;
90-
val32 |= (u32)val << 16;
91-
break;
92-
case 0:
93-
default:
94-
val32 &= ~0xFFFF;
95-
val32 |= val;
96-
break;
97-
}
98-
writel(val32, addr + (offset & ~0x3));
99-
}
100-
101-
static inline void xgene_pcie_cfg_out8(void __iomem *addr, int offset, u8 val)
102-
{
103-
u32 val32 = readl(addr + (offset & ~0x3));
104-
105-
switch (offset & 0x3) {
106-
case 0:
107-
val32 &= ~0xFF;
108-
val32 |= val;
109-
break;
110-
case 1:
111-
val32 &= ~0xFF00;
112-
val32 |= (u32)val << 8;
113-
break;
114-
case 2:
115-
val32 &= ~0xFF0000;
116-
val32 |= (u32)val << 16;
117-
break;
118-
case 3:
119-
default:
120-
val32 &= ~0xFF000000;
121-
val32 |= (u32)val << 24;
122-
break;
123-
}
124-
writel(val32, addr + (offset & ~0x3));
125-
}
126-
127-
static inline void xgene_pcie_cfg_in32(void __iomem *addr, int offset, u32 *val)
128-
{
129-
*val = readl(addr + offset);
130-
}
131-
132-
static inline void xgene_pcie_cfg_in16(void __iomem *addr, int offset, u32 *val)
133-
{
134-
*val = readl(addr + (offset & ~0x3));
135-
136-
switch (offset & 0x3) {
137-
case 2:
138-
*val >>= 16;
139-
break;
140-
}
141-
142-
*val &= 0xFFFF;
143-
}
144-
145-
static inline void xgene_pcie_cfg_in8(void __iomem *addr, int offset, u32 *val)
146-
{
147-
*val = readl(addr + (offset & ~0x3));
148-
149-
switch (offset & 0x3) {
150-
case 3:
151-
*val = *val >> 24;
152-
break;
153-
case 2:
154-
*val = *val >> 16;
155-
break;
156-
case 1:
157-
*val = *val >> 8;
158-
break;
159-
}
160-
*val &= 0xFF;
161-
}
162-
16377
/*
16478
* When the address bit [17:16] is 2'b01, the Configuration access will be
16579
* treated as Type 1 and it will be forwarded to external PCIe device.
@@ -213,69 +127,23 @@ static bool xgene_pcie_hide_rc_bars(struct pci_bus *bus, int offset)
213127
return false;
214128
}
215129

216-
static int xgene_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
217-
int offset, int len, u32 *val)
218-
{
219-
struct xgene_pcie_port *port = bus->sysdata;
220-
void __iomem *addr;
221-
222-
if ((pci_is_root_bus(bus) && devfn != 0) || !port->link_up)
223-
return PCIBIOS_DEVICE_NOT_FOUND;
224-
225-
if (xgene_pcie_hide_rc_bars(bus, offset)) {
226-
*val = 0;
227-
return PCIBIOS_SUCCESSFUL;
228-
}
229-
230-
xgene_pcie_set_rtdid_reg(bus, devfn);
231-
addr = xgene_pcie_get_cfg_base(bus);
232-
switch (len) {
233-
case 1:
234-
xgene_pcie_cfg_in8(addr, offset, val);
235-
break;
236-
case 2:
237-
xgene_pcie_cfg_in16(addr, offset, val);
238-
break;
239-
default:
240-
xgene_pcie_cfg_in32(addr, offset, val);
241-
break;
242-
}
243-
244-
return PCIBIOS_SUCCESSFUL;
245-
}
246-
247-
static int xgene_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
248-
int offset, int len, u32 val)
130+
static int xgene_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
131+
int offset)
249132
{
250133
struct xgene_pcie_port *port = bus->sysdata;
251-
void __iomem *addr;
252134

253-
if ((pci_is_root_bus(bus) && devfn != 0) || !port->link_up)
254-
return PCIBIOS_DEVICE_NOT_FOUND;
255-
256-
if (xgene_pcie_hide_rc_bars(bus, offset))
257-
return PCIBIOS_SUCCESSFUL;
135+
if ((pci_is_root_bus(bus) && devfn != 0) || !port->link_up ||
136+
xgene_pcie_hide_rc_bars(bus, offset))
137+
return NULL;
258138

259139
xgene_pcie_set_rtdid_reg(bus, devfn);
260-
addr = xgene_pcie_get_cfg_base(bus);
261-
switch (len) {
262-
case 1:
263-
xgene_pcie_cfg_out8(addr, offset, (u8)val);
264-
break;
265-
case 2:
266-
xgene_pcie_cfg_out16(addr, offset, (u16)val);
267-
break;
268-
default:
269-
xgene_pcie_cfg_out32(addr, offset, val);
270-
break;
271-
}
272-
273-
return PCIBIOS_SUCCESSFUL;
140+
return xgene_pcie_get_cfg_base(bus);
274141
}
275142

276143
static struct pci_ops xgene_pcie_ops = {
277-
.read = xgene_pcie_read_config,
278-
.write = xgene_pcie_write_config
144+
.map_bus = xgene_pcie_map_bus,
145+
.read = pci_generic_config_read32,
146+
.write = pci_generic_config_write32,
279147
};
280148

281149
static u64 xgene_pcie_set_ib_mask(void __iomem *csr_base, u32 addr,

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