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Merge tag 'v6.1-p1' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
Pull crypto updates from Herbert Xu: "API: - Feed untrusted RNGs into /dev/random - Allow HWRNG sleeping to be more interruptible - Create lib/utils module - Setting private keys no longer required for akcipher - Remove tcrypt mode=1000 - Reorganised Kconfig entries Algorithms: - Load x86/sha512 based on CPU features - Add AES-NI/AVX/x86_64/GFNI assembler implementation of aria cipher Drivers: - Add HACE crypto driver aspeed" * tag 'v6.1-p1' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: (124 commits) crypto: aspeed - Remove redundant dev_err call crypto: scatterwalk - Remove unused inline function scatterwalk_aligned() crypto: aead - Remove unused inline functions from aead crypto: bcm - Simplify obtain the name for cipher crypto: marvell/octeontx - use sysfs_emit() to instead of scnprintf() hwrng: core - start hwrng kthread also for untrusted sources crypto: zip - remove the unneeded result variable crypto: qat - add limit to linked list parsing crypto: octeontx2 - Remove the unneeded result variable crypto: ccp - Remove the unneeded result variable crypto: aspeed - Fix check for platform_get_irq() errors crypto: virtio - fix memory-leak crypto: cavium - prevent integer overflow loading firmware crypto: marvell/octeontx - prevent integer overflows crypto: aspeed - fix build error when only CRYPTO_DEV_ASPEED is enabled crypto: hisilicon/qm - fix the qos value initialization crypto: sun4i-ss - use DEFINE_SHOW_ATTRIBUTE to simplify sun4i_ss_debugfs crypto: tcrypt - add async speed test for aria cipher crypto: aria-avx - add AES-NI/AVX/x86_64/GFNI assembler implementation of aria cipher crypto: aria - prepare generic module for optimized implementations ...
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/crypto/aspeed,ast2500-hace.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: ASPEED HACE hash and crypto Hardware Accelerator Engines
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maintainers:
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- Neal Liu <neal_liu@aspeedtech.com>
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description: |
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The Hash and Crypto Engine (HACE) is designed to accelerate the throughput
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of hash data digest, encryption, and decryption. Basically, HACE can be
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divided into two independently engines - Hash Engine and Crypto Engine.
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properties:
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compatible:
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enum:
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- aspeed,ast2500-hace
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- aspeed,ast2600-hace
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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interrupts:
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maxItems: 1
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resets:
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maxItems: 1
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required:
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- compatible
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- reg
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- clocks
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- interrupts
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- resets
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/ast2600-clock.h>
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hace: crypto@1e6d0000 {
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compatible = "aspeed,ast2600-hace";
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reg = <0x1e6d0000 0x200>;
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interrupts = <4>;
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clocks = <&syscon ASPEED_CLK_GATE_YCLK>;
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resets = <&syscon ASPEED_RESET_HACE>;
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};

Documentation/virt/kvm/x86/amd-memory-encryption.rst

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The firmware can be initialized either by using its own non-volatile storage or
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the OS can manage the NV storage for the firmware using the module parameter
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``init_ex_path``. The file specified by ``init_ex_path`` must exist. To create
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a new NV storage file allocate the file with 32KB bytes of 0xFF as required by
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the SEV spec.
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``init_ex_path``. If the file specified by ``init_ex_path`` does not exist or
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is invalid, the OS will create or override the file with output from PSP.
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Returns: 0 on success, -negative on error
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MAINTAINERS

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F: Documentation/devicetree/bindings/usb/aspeed,ast2600-udc.yaml
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F: drivers/usb/gadget/udc/aspeed_udc.c
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ASPEED CRYPTO DRIVER
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M: Neal Liu <neal_liu@aspeedtech.com>
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L: linux-aspeed@lists.ozlabs.org (moderated for non-subscribers)
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S: Maintained
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F: Documentation/devicetree/bindings/crypto/aspeed,ast2500-hace.yaml
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F: drivers/crypto/aspeed/
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ASUS NOTEBOOKS AND EEEPC ACPI/WMI EXTRAS DRIVERS
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M: Corentin Chary <corentin.chary@gmail.com>
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L: acpi4asus-user@lists.sourceforge.net

arch/arm/Kconfig

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endmenu
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if CRYPTO
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source "arch/arm/crypto/Kconfig"
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endif
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source "arch/arm/Kconfig.assembler"

arch/arm/boot/dts/aspeed-g5.dtsi

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quality = <100>;
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};
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hace: crypto@1e6e3000 {
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compatible = "aspeed,ast2500-hace";
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reg = <0x1e6e3000 0x100>;
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interrupts = <4>;
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clocks = <&syscon ASPEED_CLK_GATE_YCLK>;
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resets = <&syscon ASPEED_RESET_HACE>;
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};
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gfx: display@1e6e6000 {
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compatible = "aspeed,ast2500-gfx", "syscon";
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reg = <0x1e6e6000 0x1000>;

arch/arm/boot/dts/aspeed-g6.dtsi

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#size-cells = <1>;
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ranges;
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hace: crypto@1e6d0000 {
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compatible = "aspeed,ast2600-hace";
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reg = <0x1e6d0000 0x200>;
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&syscon ASPEED_CLK_GATE_YCLK>;
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resets = <&syscon ASPEED_RESET_HACE>;
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};
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syscon: syscon@1e6e2000 {
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compatible = "aspeed,ast2600-scu", "syscon", "simple-mfd";
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reg = <0x1e6e2000 0x1000>;

arch/arm/configs/exynos_defconfig

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CONFIG_PM_DEBUG=y
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CONFIG_PM_ADVANCED_DEBUG=y
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CONFIG_ENERGY_MODEL=y
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CONFIG_ARM_CRYPTO=y
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CONFIG_CRYPTO_SHA1_ARM_NEON=m
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CONFIG_CRYPTO_SHA256_ARM=m
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CONFIG_CRYPTO_SHA512_ARM=m

arch/arm/configs/milbeaut_m10v_defconfig

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CONFIG_VFP=y
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CONFIG_NEON=y
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CONFIG_KERNEL_MODE_NEON=y
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CONFIG_ARM_CRYPTO=y
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CONFIG_CRYPTO_SHA1_ARM_NEON=m
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CONFIG_CRYPTO_SHA1_ARM_CE=m
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CONFIG_CRYPTO_SHA2_ARM_CE=m

arch/arm/configs/multi_v7_defconfig

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CONFIG_ARM_TEGRA_CPUIDLE=y
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CONFIG_ARM_QCOM_SPM_CPUIDLE=y
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CONFIG_KERNEL_MODE_NEON=y
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CONFIG_ARM_CRYPTO=y
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CONFIG_CRYPTO_SHA1_ARM_NEON=m
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CONFIG_CRYPTO_SHA1_ARM_CE=m
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CONFIG_CRYPTO_SHA2_ARM_CE=m

arch/arm/configs/omap2plus_defconfig

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CONFIG_ARM_CPUIDLE=y
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CONFIG_KERNEL_MODE_NEON=y
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CONFIG_PM_DEBUG=y
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CONFIG_ARM_CRYPTO=y
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CONFIG_CRYPTO_SHA1_ARM_NEON=m
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CONFIG_CRYPTO_SHA256_ARM=m
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CONFIG_CRYPTO_SHA512_ARM=m

arch/arm/configs/pxa_defconfig

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CONFIG_ARM_PXA2xx_CPUFREQ=m
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CONFIG_CPU_IDLE=y
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CONFIG_ARM_CPUIDLE=y
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CONFIG_ARM_CRYPTO=y
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CONFIG_CRYPTO_SHA1_ARM=m
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CONFIG_CRYPTO_SHA256_ARM=m
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CONFIG_CRYPTO_SHA512_ARM=m

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