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atenartdavem330
atenart
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davem330
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net: mvpp2: initialize the GMAC when using a port
This adds a routine to initialize the GMAC at the port level when using a port. This wasn't done until this commit, and the mvpp2 driver was relying on the bootloader/firmware initialization. This doesn't mean everything is configured in the mvpp2 driver now, but it helps reducing the gap. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Tested-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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1 file changed

+98
-25
lines changed
  • drivers/net/ethernet/marvell

1 file changed

+98
-25
lines changed

‎drivers/net/ethernet/marvell/mvpp2.c

Lines changed: 98 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -315,6 +315,7 @@
315315
/* Per-port registers */
316316
#define MVPP2_GMAC_CTRL_0_REG 0x0
317317
#define MVPP2_GMAC_PORT_EN_MASK BIT(0)
318+
#define MVPP2_GMAC_PORT_TYPE_MASK BIT(1)
318319
#define MVPP2_GMAC_MAX_RX_SIZE_OFFS 2
319320
#define MVPP2_GMAC_MAX_RX_SIZE_MASK 0x7ffc
320321
#define MVPP2_GMAC_MIB_CNTR_EN_MASK BIT(15)
@@ -326,16 +327,21 @@
326327
#define MVPP2_GMAC_SA_LOW_OFFS 7
327328
#define MVPP2_GMAC_CTRL_2_REG 0x8
328329
#define MVPP2_GMAC_INBAND_AN_MASK BIT(0)
330+
#define MVPP2_GMAC_FLOW_CTRL_MASK GENMASK(2, 1)
329331
#define MVPP2_GMAC_PCS_ENABLE_MASK BIT(3)
330332
#define MVPP2_GMAC_PORT_RGMII_MASK BIT(4)
333+
#define MVPP2_GMAC_DISABLE_PADDING BIT(5)
331334
#define MVPP2_GMAC_PORT_RESET_MASK BIT(6)
332335
#define MVPP2_GMAC_AUTONEG_CONFIG 0xc
333336
#define MVPP2_GMAC_FORCE_LINK_DOWN BIT(0)
334337
#define MVPP2_GMAC_FORCE_LINK_PASS BIT(1)
338+
#define MVPP2_GMAC_IN_BAND_AUTONEG BIT(2)
339+
#define MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS BIT(3)
335340
#define MVPP2_GMAC_CONFIG_MII_SPEED BIT(5)
336341
#define MVPP2_GMAC_CONFIG_GMII_SPEED BIT(6)
337342
#define MVPP2_GMAC_AN_SPEED_EN BIT(7)
338343
#define MVPP2_GMAC_FC_ADV_EN BIT(9)
344+
#define MVPP2_GMAC_FLOW_CTRL_AUTONEG BIT(11)
339345
#define MVPP2_GMAC_CONFIG_FULL_DUPLEX BIT(12)
340346
#define MVPP2_GMAC_AN_DUPLEX_EN BIT(13)
341347
#define MVPP2_GMAC_PORT_FIFO_CFG_1_REG 0x1c
@@ -4245,6 +4251,92 @@ mvpp2_shared_interrupt_mask_unmask(struct mvpp2_port *port, bool mask)
42454251

42464252
/* Port configuration routines */
42474253

4254+
static void mvpp2_port_mii_gmac_configure_mode(struct mvpp2_port *port)
4255+
{
4256+
u32 val;
4257+
4258+
if (port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
4259+
val = readl(port->base + MVPP22_GMAC_CTRL_4_REG);
4260+
val |= MVPP22_CTRL4_SYNC_BYPASS_DIS | MVPP22_CTRL4_DP_CLK_SEL |
4261+
MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE;
4262+
val &= ~MVPP22_CTRL4_EXT_PIN_GMII_SEL;
4263+
writel(val, port->base + MVPP22_GMAC_CTRL_4_REG);
4264+
4265+
val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
4266+
val |= MVPP2_GMAC_DISABLE_PADDING;
4267+
val &= ~MVPP2_GMAC_FLOW_CTRL_MASK;
4268+
writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
4269+
} else if (port->phy_interface == PHY_INTERFACE_MODE_RGMII ||
4270+
port->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
4271+
port->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID ||
4272+
port->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) {
4273+
val = readl(port->base + MVPP22_GMAC_CTRL_4_REG);
4274+
val |= MVPP22_CTRL4_EXT_PIN_GMII_SEL |
4275+
MVPP22_CTRL4_SYNC_BYPASS_DIS |
4276+
MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE;
4277+
val &= ~MVPP22_CTRL4_DP_CLK_SEL;
4278+
writel(val, port->base + MVPP22_GMAC_CTRL_4_REG);
4279+
4280+
val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
4281+
val &= ~MVPP2_GMAC_DISABLE_PADDING;
4282+
writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
4283+
}
4284+
4285+
/* The port is connected to a copper PHY */
4286+
val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
4287+
val &= ~MVPP2_GMAC_PORT_TYPE_MASK;
4288+
writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
4289+
4290+
val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4291+
val |= MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS |
4292+
MVPP2_GMAC_AN_SPEED_EN | MVPP2_GMAC_FLOW_CTRL_AUTONEG |
4293+
MVPP2_GMAC_AN_DUPLEX_EN;
4294+
if (port->phy_interface == PHY_INTERFACE_MODE_SGMII)
4295+
val |= MVPP2_GMAC_IN_BAND_AUTONEG;
4296+
writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4297+
}
4298+
4299+
static void mvpp2_port_mii_gmac_configure(struct mvpp2_port *port)
4300+
{
4301+
u32 val;
4302+
4303+
/* Force link down */
4304+
val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4305+
val &= ~MVPP2_GMAC_FORCE_LINK_PASS;
4306+
val |= MVPP2_GMAC_FORCE_LINK_DOWN;
4307+
writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4308+
4309+
/* Set the GMAC in a reset state */
4310+
val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
4311+
val |= MVPP2_GMAC_PORT_RESET_MASK;
4312+
writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
4313+
4314+
/* Configure the PCS and in-band AN */
4315+
val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
4316+
if (port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
4317+
val |= MVPP2_GMAC_INBAND_AN_MASK | MVPP2_GMAC_PCS_ENABLE_MASK;
4318+
} else if (port->phy_interface == PHY_INTERFACE_MODE_RGMII ||
4319+
port->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
4320+
port->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID ||
4321+
port->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) {
4322+
val &= ~MVPP2_GMAC_PCS_ENABLE_MASK;
4323+
val |= MVPP2_GMAC_PORT_RGMII_MASK;
4324+
}
4325+
writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
4326+
4327+
mvpp2_port_mii_gmac_configure_mode(port);
4328+
4329+
/* Unset the GMAC reset state */
4330+
val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
4331+
val &= ~MVPP2_GMAC_PORT_RESET_MASK;
4332+
writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
4333+
4334+
/* Stop forcing link down */
4335+
val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4336+
val &= ~MVPP2_GMAC_FORCE_LINK_DOWN;
4337+
writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4338+
}
4339+
42484340
static void mvpp22_port_mii_set(struct mvpp2_port *port)
42494341
{
42504342
u32 val;
@@ -4262,38 +4354,19 @@ static void mvpp22_port_mii_set(struct mvpp2_port *port)
42624354

42634355
writel(val, port->base + MVPP22_XLG_CTRL3_REG);
42644356
}
4265-
4266-
val = readl(port->base + MVPP22_GMAC_CTRL_4_REG);
4267-
if (port->phy_interface == PHY_INTERFACE_MODE_RGMII)
4268-
val |= MVPP22_CTRL4_EXT_PIN_GMII_SEL;
4269-
else
4270-
val &= ~MVPP22_CTRL4_EXT_PIN_GMII_SEL;
4271-
val &= ~MVPP22_CTRL4_DP_CLK_SEL;
4272-
val |= MVPP22_CTRL4_SYNC_BYPASS_DIS;
4273-
val |= MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE;
4274-
writel(val, port->base + MVPP22_GMAC_CTRL_4_REG);
42754357
}
42764358

42774359
static void mvpp2_port_mii_set(struct mvpp2_port *port)
42784360
{
4279-
u32 val;
4280-
42814361
if (port->priv->hw_version == MVPP22)
42824362
mvpp22_port_mii_set(port);
42834363

4284-
val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
4285-
4286-
switch (port->phy_interface) {
4287-
case PHY_INTERFACE_MODE_SGMII:
4288-
val |= MVPP2_GMAC_INBAND_AN_MASK;
4289-
break;
4290-
case PHY_INTERFACE_MODE_RGMII:
4291-
val |= MVPP2_GMAC_PORT_RGMII_MASK;
4292-
default:
4293-
val &= ~MVPP2_GMAC_PCS_ENABLE_MASK;
4294-
}
4295-
4296-
writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
4364+
if (port->phy_interface == PHY_INTERFACE_MODE_RGMII ||
4365+
port->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
4366+
port->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID ||
4367+
port->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID ||
4368+
port->phy_interface == PHY_INTERFACE_MODE_SGMII)
4369+
mvpp2_port_mii_gmac_configure(port);
42974370
}
42984371

42994372
static void mvpp2_port_fc_adv_enable(struct mvpp2_port *port)

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