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Merge branches 'pm-cpuidle', 'pm-cpufreq' and 'pm-cpufreq-sched'
* pm-cpuidle: cpuidle: Add 'above' and 'below' idle state metrics cpuidle: big.LITTLE: fix refcount leak cpuidle: Add cpuidle.governor= command line parameter cpuidle: poll_state: Disregard disable idle states Documentation: admin-guide: PM: Add cpuidle document * pm-cpufreq: cpufreq: qcom-hw: Add support for QCOM cpufreq HW driver dt-bindings: cpufreq: Introduce QCOM cpufreq firmware bindings cpufreq: nforce2: Remove meaningless return cpufreq: ia64: Remove unused header files cpufreq: imx6q: save one condition block for normal case of nvmem read cpufreq: imx6q: remove unused code cpufreq: pmac64: add of_node_put() cpufreq: powernv: add of_node_put() Documentation: intel_pstate: Clarify coordination of P-State limits cpufreq: intel_pstate: Force HWP min perf before offline cpufreq: s3c24xx: Change to use DEFINE_SHOW_ATTRIBUTE macro * pm-cpufreq-sched: sched/cpufreq: Add the SPDX tags
4 parents 7edcbbf + 04dab58 + 2849dd8 + 108c35a commit 3a56fe6

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‎Documentation/ABI/testing/sysfs-devices-system-cpu

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@@ -145,6 +145,8 @@ What: /sys/devices/system/cpu/cpuX/cpuidle/stateN/name
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/sys/devices/system/cpu/cpuX/cpuidle/stateN/power
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/sys/devices/system/cpu/cpuX/cpuidle/stateN/time
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/sys/devices/system/cpu/cpuX/cpuidle/stateN/usage
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/sys/devices/system/cpu/cpuX/cpuidle/stateN/above
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/sys/devices/system/cpu/cpuX/cpuidle/stateN/below
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Date: September 2007
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KernelVersion: v2.6.24
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Contact: Linux power management list <linux-pm@vger.kernel.org>
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usage: (RO) Number of times this state was entered (a count).
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above: (RO) Number of times this state was entered, but the
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observed CPU idle duration was too short for it (a count).
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below: (RO) Number of times this state was entered, but the
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observed CPU idle duration was too long for it (a count).
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What: /sys/devices/system/cpu/cpuX/cpuidle/stateN/desc
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Date: February 2008

‎Documentation/admin-guide/kernel-parameters.txt

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cpuidle.off=1 [CPU_IDLE]
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disable the cpuidle sub-system
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cpuidle.governor=
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[CPU_IDLE] Name of the cpuidle governor to use.
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cpufreq.off=1 [CPU_FREQ]
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disable the cpufreq sub-system
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‎Documentation/admin-guide/pm/cpuidle.rst

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‎Documentation/admin-guide/pm/intel_pstate.rst

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@@ -495,7 +495,15 @@ on the following rules, regardless of the current operation mode of the driver:
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2. Each individual CPU is affected by its own per-policy limits (that is, it
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cannot be requested to run faster than its own per-policy maximum and it
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cannot be requested to run slower than its own per-policy minimum).
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cannot be requested to run slower than its own per-policy minimum). The
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effective performance depends on whether the platform supports per core
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P-states, hyper-threading is enabled and on current performance requests
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from other CPUs. When platform doesn't support per core P-states, the
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effective performance can be more than the policy limits set on a CPU, if
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other CPUs are requesting higher performance at that moment. Even with per
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core P-states support, when hyper-threading is enabled, if the sibling CPU
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is requesting higher performance, the other siblings will get higher
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performance than their policy limits.
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3. The global and per-policy limits can be set independently.
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‎Documentation/admin-guide/pm/working-state.rst

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@@ -5,5 +5,6 @@ Working-State Power Management
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.. toctree::
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:maxdepth: 2
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cpuidle
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cpufreq
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intel_pstate

‎Documentation/cpuidle/core.txt

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‎Documentation/cpuidle/sysfs.txt

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‎Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt

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Qualcomm Technologies, Inc. CPUFREQ Bindings
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CPUFREQ HW is a hardware engine used by some Qualcomm Technologies, Inc. (QTI)
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SoCs to manage frequency in hardware. It is capable of controlling frequency
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for multiple clusters.
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Properties:
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- compatible
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Usage: required
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Value type: <string>
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Definition: must be "qcom,cpufreq-hw".
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- clocks
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Usage: required
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Value type: <phandle> From common clock binding.
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Definition: clock handle for XO clock and GPLL0 clock.
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- clock-names
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Usage: required
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Value type: <string> From common clock binding.
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Definition: must be "xo", "alternate".
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- reg
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Usage: required
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Value type: <prop-encoded-array>
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Definition: Addresses and sizes for the memory of the HW bases in
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each frequency domain.
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- reg-names
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Usage: Optional
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Value type: <string>
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Definition: Frequency domain name i.e.
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"freq-domain0", "freq-domain1".
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- #freq-domain-cells:
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Usage: required.
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Definition: Number of cells in a freqency domain specifier.
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* Property qcom,freq-domain
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Devices supporting freq-domain must set their "qcom,freq-domain" property with
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phandle to a cpufreq_hw followed by the Domain ID(0/1) in the CPU DT node.
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Example:
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Example 1: Dual-cluster, Quad-core per cluster. CPUs within a cluster switch
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DCVS state together.
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/ {
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "qcom,kryo385";
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reg = <0x0 0x0>;
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enable-method = "psci";
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next-level-cache = <&L2_0>;
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qcom,freq-domain = <&cpufreq_hw 0>;
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L2_0: l2-cache {
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compatible = "cache";
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next-level-cache = <&L3_0>;
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L3_0: l3-cache {
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compatible = "cache";
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};
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};
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};
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CPU1: cpu@100 {
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device_type = "cpu";
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compatible = "qcom,kryo385";
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reg = <0x0 0x100>;
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enable-method = "psci";
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next-level-cache = <&L2_100>;
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qcom,freq-domain = <&cpufreq_hw 0>;
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L2_100: l2-cache {
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compatible = "cache";
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next-level-cache = <&L3_0>;
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};
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};
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CPU2: cpu@200 {
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device_type = "cpu";
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compatible = "qcom,kryo385";
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reg = <0x0 0x200>;
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enable-method = "psci";
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next-level-cache = <&L2_200>;
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qcom,freq-domain = <&cpufreq_hw 0>;
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L2_200: l2-cache {
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compatible = "cache";
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next-level-cache = <&L3_0>;
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};
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};
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CPU3: cpu@300 {
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device_type = "cpu";
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compatible = "qcom,kryo385";
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reg = <0x0 0x300>;
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enable-method = "psci";
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next-level-cache = <&L2_300>;
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qcom,freq-domain = <&cpufreq_hw 0>;
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L2_300: l2-cache {
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compatible = "cache";
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next-level-cache = <&L3_0>;
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};
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};
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CPU4: cpu@400 {
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device_type = "cpu";
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compatible = "qcom,kryo385";
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reg = <0x0 0x400>;
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enable-method = "psci";
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next-level-cache = <&L2_400>;
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qcom,freq-domain = <&cpufreq_hw 1>;
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L2_400: l2-cache {
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compatible = "cache";
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next-level-cache = <&L3_0>;
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};
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};
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CPU5: cpu@500 {
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device_type = "cpu";
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compatible = "qcom,kryo385";
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reg = <0x0 0x500>;
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enable-method = "psci";
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next-level-cache = <&L2_500>;
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qcom,freq-domain = <&cpufreq_hw 1>;
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L2_500: l2-cache {
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compatible = "cache";
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next-level-cache = <&L3_0>;
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};
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};
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CPU6: cpu@600 {
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device_type = "cpu";
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compatible = "qcom,kryo385";
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reg = <0x0 0x600>;
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enable-method = "psci";
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next-level-cache = <&L2_600>;
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qcom,freq-domain = <&cpufreq_hw 1>;
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L2_600: l2-cache {
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compatible = "cache";
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next-level-cache = <&L3_0>;
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};
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};
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CPU7: cpu@700 {
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device_type = "cpu";
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compatible = "qcom,kryo385";
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reg = <0x0 0x700>;
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enable-method = "psci";
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next-level-cache = <&L2_700>;
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qcom,freq-domain = <&cpufreq_hw 1>;
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L2_700: l2-cache {
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compatible = "cache";
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next-level-cache = <&L3_0>;
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};
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};
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};
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soc {
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cpufreq_hw: cpufreq@17d43000 {
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compatible = "qcom,cpufreq-hw";
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reg = <0x17d43000 0x1400>, <0x17d45800 0x1400>;
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reg-names = "freq-domain0", "freq-domain1";
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clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
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clock-names = "xo", "alternate";
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#freq-domain-cells = <1>;
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};
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}

‎drivers/cpufreq/Kconfig.arm

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If in doubt, say N.
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config ARM_QCOM_CPUFREQ_HW
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tristate "QCOM CPUFreq HW driver"
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depends on ARCH_QCOM || COMPILE_TEST
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help
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Support for the CPUFreq HW driver.
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Some QCOM chipsets have a HW engine to offload the steps
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necessary for changing the frequency of the CPUs. Firmware loaded
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in this engine exposes a programming interface to the OS.
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The driver implements the cpufreq interface for this HW engine.
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Say Y if you want to support CPUFreq HW.
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config ARM_S3C_CPUFREQ
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bool
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help

‎drivers/cpufreq/Makefile

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@@ -61,6 +61,7 @@ obj-$(CONFIG_MACH_MVEBU_V7) += mvebu-cpufreq.o
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obj-$(CONFIG_ARM_OMAP2PLUS_CPUFREQ) += omap-cpufreq.o
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obj-$(CONFIG_ARM_PXA2xx_CPUFREQ) += pxa2xx-cpufreq.o
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obj-$(CONFIG_PXA3xx) += pxa3xx-cpufreq.o
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obj-$(CONFIG_ARM_QCOM_CPUFREQ_HW) += qcom-cpufreq-hw.o
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obj-$(CONFIG_ARM_QCOM_CPUFREQ_KRYO) += qcom-cpufreq-kryo.o
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obj-$(CONFIG_ARM_S3C2410_CPUFREQ) += s3c2410-cpufreq.o
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obj-$(CONFIG_ARM_S3C2412_CPUFREQ) += s3c2412-cpufreq.o

‎drivers/cpufreq/cpufreq-nforce2.c

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/* Now write the value in all 64 registers */
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for (temp = 0; temp <= 0x3f; temp++)
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pci_write_config_dword(nforce2_dev, NFORCE2_PLLREG, pll);
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}
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/**
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module_init(nforce2_init);
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module_exit(nforce2_exit);
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