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drm/i915/execlists: Move bdw GPGPU w/a to emit_bb
Move the re-enabling of MI arbitration from a per-bb w/a buffer to the emission of the batch buffer itself. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171003203453.15692-5-chris@chris-wilson.co.uk
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drivers/gpu/drm/i915/intel_lrc.c

Lines changed: 4 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -1158,24 +1158,6 @@ static u32 *gen8_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
11581158
return batch;
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}
11601160

1161-
/*
1162-
* This batch is started immediately after indirect_ctx batch. Since we ensure
1163-
* that indirect_ctx ends on a cacheline this batch is aligned automatically.
1164-
*
1165-
* The number of DWORDS written are returned using this field.
1166-
*
1167-
* This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding
1168-
* to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant.
1169-
*/
1170-
static u32 *gen8_init_perctx_bb(struct intel_engine_cs *engine, u32 *batch)
1171-
{
1172-
/* WaDisableCtxRestoreArbitration:bdw,chv */
1173-
*batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
1174-
*batch++ = MI_BATCH_BUFFER_END;
1175-
1176-
return batch;
1177-
}
1178-
11791161
static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
11801162
{
11811163
/* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt,glk */
@@ -1290,7 +1272,7 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
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break;
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case 8:
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wa_bb_fn[0] = gen8_init_indirectctx_bb;
1293-
wa_bb_fn[1] = gen8_init_perctx_bb;
1275+
wa_bb_fn[1] = NULL;
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break;
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default:
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MISSING_CASE(INTEL_GEN(engine->i915));
@@ -1534,13 +1516,15 @@ static int gen8_emit_bb_start(struct drm_i915_gem_request *req,
15341516
if (IS_ERR(cs))
15351517
return PTR_ERR(cs);
15361518

1519+
/* WaDisableCtxRestoreArbitration:bdw,chv */
1520+
*cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
1521+
15371522
/* FIXME(BDW): Address space and security selectors. */
15381523
*cs++ = MI_BATCH_BUFFER_START_GEN8 |
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(flags & I915_DISPATCH_SECURE ? 0 : BIT(8)) |
15401525
(flags & I915_DISPATCH_RS ? MI_BATCH_RESOURCE_STREAMER : 0);
15411526
*cs++ = lower_32_bits(offset);
15421527
*cs++ = upper_32_bits(offset);
1543-
*cs++ = MI_NOOP;
15441528
intel_ring_advance(req, cs);
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15461530
return 0;

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