usb: chipidea: Fix Internal error: : 808 [#1] ARM related to STS flag

ruehlchris · gregkh · commit 3b5d3e6845bf · 2014-01-13T15:55:19.000-08:00
* init the sts flag to 0 (missed)
* fix write the real bit not sts value
* Set PORTCS_STS and DEVLC_STS only if sts = 1

[Peter Chen: This one and the next patch fix the problem occurred imx27
and imx31, and imx27 and imx31 usb support are enabled until 3.14, so
these two patches isn't needed for -stable]

Signed-off-by: Chris Ruehl &lt;chris.ruehl@gtsys.com.hk&gt;
Signed-off-by: Peter Chen &lt;peter.chen@freescale.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
diff --git a/drivers/usb/chipidea/core.c b/drivers/usb/chipidea/core.c
@@ -236,7 +236,7 @@ static int hw_device_init(struct ci_hdrc *ci, void __iomem *base)
 
 static void hw_phymode_configure(struct ci_hdrc *ci)
 {
-	u32 portsc, lpm, sts;
+	u32 portsc, lpm, sts = 0;
 
 	switch (ci->platdata->phy_mode) {
 	case USBPHY_INTERFACE_MODE_UTMI:
@@ -266,10 +266,12 @@ static void hw_phymode_configure(struct ci_hdrc *ci)
 
 	if (ci->hw_bank.lpm) {
 		hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm);
-		hw_write(ci, OP_DEVLC, DEVLC_STS, sts);
+		if (sts)
+			hw_write(ci, OP_DEVLC, DEVLC_STS, DEVLC_STS);
 	} else {
 		hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc);
-		hw_write(ci, OP_PORTSC, PORTSC_STS, sts);
+		if (sts)
+			hw_write(ci, OP_PORTSC, PORTSC_STS, PORTSC_STS);
 	}
 }
 

Original file line number	Diff line number	Diff line change
`@@ -236,7 +236,7 @@ static int hw_device_init(struct ci_hdrc ci, void __iomem base)`
`236`	`236`
`237`	`237`	`static void hw_phymode_configure(struct ci_hdrc *ci)`
`238`	`238`	`{`
`239`		`- u32 portsc, lpm, sts;`
	`239`	`+ u32 portsc, lpm, sts = 0;`
`240`	`240`
`241`	`241`	`switch (ci->platdata->phy_mode) {`
`242`	`242`	`case USBPHY_INTERFACE_MODE_UTMI:`
`@@ -266,10 +266,12 @@ static void hw_phymode_configure(struct ci_hdrc *ci)`
`266`	`266`
`267`	`267`	`if (ci->hw_bank.lpm) {`
`268`	`268`	`hw_write(ci, OP_DEVLC, DEVLC_PTS(7) \| DEVLC_PTW, lpm);`
`269`		`- hw_write(ci, OP_DEVLC, DEVLC_STS, sts);`
	`269`	`+ if (sts)`
	`270`	`+ hw_write(ci, OP_DEVLC, DEVLC_STS, DEVLC_STS);`
`270`	`271`	`} else {`
`271`	`272`	`hw_write(ci, OP_PORTSC, PORTSC_PTS(7) \| PORTSC_PTW, portsc);`
`272`		`- hw_write(ci, OP_PORTSC, PORTSC_STS, sts);`
	`273`	`+ if (sts)`
	`274`	`+ hw_write(ci, OP_PORTSC, PORTSC_STS, PORTSC_STS);`
`273`	`275`	`}`
`274`	`276`	`}`
`275`	`277`