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davem330davem330
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Merge branch 'davem-next.mii' of git://git.kernel.org/pub/scm/linux/kernel/git/romieu/netdev-2.6
2 parents 31c15a2 + cd29678 commit 3cd0999

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4 files changed

+69
-194
lines changed

4 files changed

+69
-194
lines changed

‎drivers/net/ethernet/dlink/dl2k.c

Lines changed: 51 additions & 54 deletions
Original file line numberDiff line numberDiff line change
@@ -1428,7 +1428,7 @@ mii_wait_link (struct net_device *dev, int wait)
14281428

14291429
do {
14301430
bmsr = mii_read (dev, phy_addr, MII_BMSR);
1431-
if (bmsr & MII_BMSR_LINK_STATUS)
1431+
if (bmsr & BMSR_LSTATUS)
14321432
return 0;
14331433
mdelay (1);
14341434
} while (--wait > 0);
@@ -1449,60 +1449,60 @@ mii_get_media (struct net_device *dev)
14491449

14501450
bmsr = mii_read (dev, phy_addr, MII_BMSR);
14511451
if (np->an_enable) {
1452-
if (!(bmsr & MII_BMSR_AN_COMPLETE)) {
1452+
if (!(bmsr & BMSR_ANEGCOMPLETE)) {
14531453
/* Auto-Negotiation not completed */
14541454
return -1;
14551455
}
1456-
negotiate = mii_read (dev, phy_addr, MII_ANAR) &
1457-
mii_read (dev, phy_addr, MII_ANLPAR);
1458-
mscr = mii_read (dev, phy_addr, MII_MSCR);
1459-
mssr = mii_read (dev, phy_addr, MII_MSSR);
1460-
if (mscr & MII_MSCR_1000BT_FD && mssr & MII_MSSR_LP_1000BT_FD) {
1456+
negotiate = mii_read (dev, phy_addr, MII_ADVERTISE) &
1457+
mii_read (dev, phy_addr, MII_LPA);
1458+
mscr = mii_read (dev, phy_addr, MII_CTRL1000);
1459+
mssr = mii_read (dev, phy_addr, MII_STAT1000);
1460+
if (mscr & ADVERTISE_1000FULL && mssr & LPA_1000FULL) {
14611461
np->speed = 1000;
14621462
np->full_duplex = 1;
14631463
printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n");
1464-
} else if (mscr & MII_MSCR_1000BT_HD && mssr & MII_MSSR_LP_1000BT_HD) {
1464+
} else if (mscr & ADVERTISE_1000HALF && mssr & LPA_1000HALF) {
14651465
np->speed = 1000;
14661466
np->full_duplex = 0;
14671467
printk (KERN_INFO "Auto 1000 Mbps, Half duplex\n");
1468-
} else if (negotiate & MII_ANAR_100BX_FD) {
1468+
} else if (negotiate & ADVERTISE_100FULL) {
14691469
np->speed = 100;
14701470
np->full_duplex = 1;
14711471
printk (KERN_INFO "Auto 100 Mbps, Full duplex\n");
1472-
} else if (negotiate & MII_ANAR_100BX_HD) {
1472+
} else if (negotiate & ADVERTISE_100HALF) {
14731473
np->speed = 100;
14741474
np->full_duplex = 0;
14751475
printk (KERN_INFO "Auto 100 Mbps, Half duplex\n");
1476-
} else if (negotiate & MII_ANAR_10BT_FD) {
1476+
} else if (negotiate & ADVERTISE_10FULL) {
14771477
np->speed = 10;
14781478
np->full_duplex = 1;
14791479
printk (KERN_INFO "Auto 10 Mbps, Full duplex\n");
1480-
} else if (negotiate & MII_ANAR_10BT_HD) {
1480+
} else if (negotiate & ADVERTISE_10HALF) {
14811481
np->speed = 10;
14821482
np->full_duplex = 0;
14831483
printk (KERN_INFO "Auto 10 Mbps, Half duplex\n");
14841484
}
1485-
if (negotiate & MII_ANAR_PAUSE) {
1485+
if (negotiate & ADVERTISE_PAUSE_CAP) {
14861486
np->tx_flow &= 1;
14871487
np->rx_flow &= 1;
1488-
} else if (negotiate & MII_ANAR_ASYMMETRIC) {
1488+
} else if (negotiate & ADVERTISE_PAUSE_ASYM) {
14891489
np->tx_flow = 0;
14901490
np->rx_flow &= 1;
14911491
}
14921492
/* else tx_flow, rx_flow = user select */
14931493
} else {
14941494
__u16 bmcr = mii_read (dev, phy_addr, MII_BMCR);
1495-
switch (bmcr & (MII_BMCR_SPEED_100 | MII_BMCR_SPEED_1000)) {
1496-
case MII_BMCR_SPEED_1000:
1495+
switch (bmcr & (BMCR_SPEED100 | BMCR_SPEED1000)) {
1496+
case BMCR_SPEED1000:
14971497
printk (KERN_INFO "Operating at 1000 Mbps, ");
14981498
break;
1499-
case MII_BMCR_SPEED_100:
1499+
case BMCR_SPEED100:
15001500
printk (KERN_INFO "Operating at 100 Mbps, ");
15011501
break;
15021502
case 0:
15031503
printk (KERN_INFO "Operating at 10 Mbps, ");
15041504
}
1505-
if (bmcr & MII_BMCR_DUPLEX_MODE) {
1505+
if (bmcr & BMCR_FULLDPLX) {
15061506
printk (KERN_CONT "Full duplex\n");
15071507
} else {
15081508
printk (KERN_CONT "Half duplex\n");
@@ -1536,33 +1536,31 @@ mii_set_media (struct net_device *dev)
15361536
if (np->an_enable) {
15371537
/* Advertise capabilities */
15381538
bmsr = mii_read (dev, phy_addr, MII_BMSR);
1539-
anar = mii_read (dev, phy_addr, MII_ANAR) &
1540-
~MII_ANAR_100BX_FD &
1541-
~MII_ANAR_100BX_HD &
1542-
~MII_ANAR_100BT4 &
1543-
~MII_ANAR_10BT_FD &
1544-
~MII_ANAR_10BT_HD;
1545-
if (bmsr & MII_BMSR_100BX_FD)
1546-
anar |= MII_ANAR_100BX_FD;
1547-
if (bmsr & MII_BMSR_100BX_HD)
1548-
anar |= MII_ANAR_100BX_HD;
1549-
if (bmsr & MII_BMSR_100BT4)
1550-
anar |= MII_ANAR_100BT4;
1551-
if (bmsr & MII_BMSR_10BT_FD)
1552-
anar |= MII_ANAR_10BT_FD;
1553-
if (bmsr & MII_BMSR_10BT_HD)
1554-
anar |= MII_ANAR_10BT_HD;
1555-
anar |= MII_ANAR_PAUSE | MII_ANAR_ASYMMETRIC;
1556-
mii_write (dev, phy_addr, MII_ANAR, anar);
1539+
anar = mii_read (dev, phy_addr, MII_ADVERTISE) &
1540+
~(ADVERTISE_100FULL | ADVERTISE_10FULL |
1541+
ADVERTISE_100HALF | ADVERTISE_10HALF |
1542+
ADVERTISE_100BASE4);
1543+
if (bmsr & BMSR_100FULL)
1544+
anar |= ADVERTISE_100FULL;
1545+
if (bmsr & BMSR_100HALF)
1546+
anar |= ADVERTISE_100HALF;
1547+
if (bmsr & BMSR_100BASE4)
1548+
anar |= ADVERTISE_100BASE4;
1549+
if (bmsr & BMSR_10FULL)
1550+
anar |= ADVERTISE_10FULL;
1551+
if (bmsr & BMSR_10HALF)
1552+
anar |= ADVERTISE_10HALF;
1553+
anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1554+
mii_write (dev, phy_addr, MII_ADVERTISE, anar);
15571555

15581556
/* Enable Auto crossover */
15591557
pscr = mii_read (dev, phy_addr, MII_PHY_SCR);
15601558
pscr |= 3 << 5; /* 11'b */
15611559
mii_write (dev, phy_addr, MII_PHY_SCR, pscr);
15621560

15631561
/* Soft reset PHY */
1564-
mii_write (dev, phy_addr, MII_BMCR, MII_BMCR_RESET);
1565-
bmcr = MII_BMCR_AN_ENABLE | MII_BMCR_RESTART_AN | MII_BMCR_RESET;
1562+
mii_write (dev, phy_addr, MII_BMCR, BMCR_RESET);
1563+
bmcr = BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET;
15661564
mii_write (dev, phy_addr, MII_BMCR, bmcr);
15671565
mdelay(1);
15681566
} else {
@@ -1574,7 +1572,7 @@ mii_set_media (struct net_device *dev)
15741572

15751573
/* 2) PHY Reset */
15761574
bmcr = mii_read (dev, phy_addr, MII_BMCR);
1577-
bmcr |= MII_BMCR_RESET;
1575+
bmcr |= BMCR_RESET;
15781576
mii_write (dev, phy_addr, MII_BMCR, bmcr);
15791577

15801578
/* 3) Power Down */
@@ -1583,25 +1581,25 @@ mii_set_media (struct net_device *dev)
15831581
mdelay (100); /* wait a certain time */
15841582

15851583
/* 4) Advertise nothing */
1586-
mii_write (dev, phy_addr, MII_ANAR, 0);
1584+
mii_write (dev, phy_addr, MII_ADVERTISE, 0);
15871585

15881586
/* 5) Set media and Power Up */
1589-
bmcr = MII_BMCR_POWER_DOWN;
1587+
bmcr = BMCR_PDOWN;
15901588
if (np->speed == 100) {
1591-
bmcr |= MII_BMCR_SPEED_100;
1589+
bmcr |= BMCR_SPEED100;
15921590
printk (KERN_INFO "Manual 100 Mbps, ");
15931591
} else if (np->speed == 10) {
15941592
printk (KERN_INFO "Manual 10 Mbps, ");
15951593
}
15961594
if (np->full_duplex) {
1597-
bmcr |= MII_BMCR_DUPLEX_MODE;
1595+
bmcr |= BMCR_FULLDPLX;
15981596
printk (KERN_CONT "Full duplex\n");
15991597
} else {
16001598
printk (KERN_CONT "Half duplex\n");
16011599
}
16021600
#if 0
16031601
/* Set 1000BaseT Master/Slave setting */
1604-
mscr = mii_read (dev, phy_addr, MII_MSCR);
1602+
mscr = mii_read (dev, phy_addr, MII_CTRL1000);
16051603
mscr |= MII_MSCR_CFG_ENABLE;
16061604
mscr &= ~MII_MSCR_CFG_VALUE = 0;
16071605
#endif
@@ -1624,7 +1622,7 @@ mii_get_media_pcs (struct net_device *dev)
16241622

16251623
bmsr = mii_read (dev, phy_addr, PCS_BMSR);
16261624
if (np->an_enable) {
1627-
if (!(bmsr & MII_BMSR_AN_COMPLETE)) {
1625+
if (!(bmsr & BMSR_ANEGCOMPLETE)) {
16281626
/* Auto-Negotiation not completed */
16291627
return -1;
16301628
}
@@ -1649,7 +1647,7 @@ mii_get_media_pcs (struct net_device *dev)
16491647
} else {
16501648
__u16 bmcr = mii_read (dev, phy_addr, PCS_BMCR);
16511649
printk (KERN_INFO "Operating at 1000 Mbps, ");
1652-
if (bmcr & MII_BMCR_DUPLEX_MODE) {
1650+
if (bmcr & BMCR_FULLDPLX) {
16531651
printk (KERN_CONT "Full duplex\n");
16541652
} else {
16551653
printk (KERN_CONT "Half duplex\n");
@@ -1682,30 +1680,29 @@ mii_set_media_pcs (struct net_device *dev)
16821680
if (np->an_enable) {
16831681
/* Advertise capabilities */
16841682
esr = mii_read (dev, phy_addr, PCS_ESR);
1685-
anar = mii_read (dev, phy_addr, MII_ANAR) &
1683+
anar = mii_read (dev, phy_addr, MII_ADVERTISE) &
16861684
~PCS_ANAR_HALF_DUPLEX &
16871685
~PCS_ANAR_FULL_DUPLEX;
16881686
if (esr & (MII_ESR_1000BT_HD | MII_ESR_1000BX_HD))
16891687
anar |= PCS_ANAR_HALF_DUPLEX;
16901688
if (esr & (MII_ESR_1000BT_FD | MII_ESR_1000BX_FD))
16911689
anar |= PCS_ANAR_FULL_DUPLEX;
16921690
anar |= PCS_ANAR_PAUSE | PCS_ANAR_ASYMMETRIC;
1693-
mii_write (dev, phy_addr, MII_ANAR, anar);
1691+
mii_write (dev, phy_addr, MII_ADVERTISE, anar);
16941692

16951693
/* Soft reset PHY */
1696-
mii_write (dev, phy_addr, MII_BMCR, MII_BMCR_RESET);
1697-
bmcr = MII_BMCR_AN_ENABLE | MII_BMCR_RESTART_AN |
1698-
MII_BMCR_RESET;
1694+
mii_write (dev, phy_addr, MII_BMCR, BMCR_RESET);
1695+
bmcr = BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET;
16991696
mii_write (dev, phy_addr, MII_BMCR, bmcr);
17001697
mdelay(1);
17011698
} else {
17021699
/* Force speed setting */
17031700
/* PHY Reset */
1704-
bmcr = MII_BMCR_RESET;
1701+
bmcr = BMCR_RESET;
17051702
mii_write (dev, phy_addr, MII_BMCR, bmcr);
17061703
mdelay(10);
17071704
if (np->full_duplex) {
1708-
bmcr = MII_BMCR_DUPLEX_MODE;
1705+
bmcr = BMCR_FULLDPLX;
17091706
printk (KERN_INFO "Manual full duplex\n");
17101707
} else {
17111708
bmcr = 0;
@@ -1715,7 +1712,7 @@ mii_set_media_pcs (struct net_device *dev)
17151712
mdelay(10);
17161713

17171714
/* Advertise nothing */
1718-
mii_write (dev, phy_addr, MII_ANAR, 0);
1715+
mii_write (dev, phy_addr, MII_ADVERTISE, 0);
17191716
}
17201717
return 0;
17211718
}

‎drivers/net/ethernet/dlink/dl2k.h

Lines changed: 2 additions & 108 deletions
Original file line numberDiff line numberDiff line change
@@ -28,6 +28,7 @@
2828
#include <linux/init.h>
2929
#include <linux/crc32.h>
3030
#include <linux/ethtool.h>
31+
#include <linux/mii.h>
3132
#include <linux/bitops.h>
3233
#include <asm/processor.h> /* Processor type for cache alignment. */
3334
#include <asm/io.h>
@@ -271,20 +272,9 @@ enum RFS_bits {
271272
#define MII_RESET_TIME_OUT 10000
272273
/* MII register */
273274
enum _mii_reg {
274-
MII_BMCR = 0,
275-
MII_BMSR = 1,
276-
MII_PHY_ID1 = 2,
277-
MII_PHY_ID2 = 3,
278-
MII_ANAR = 4,
279-
MII_ANLPAR = 5,
280-
MII_ANER = 6,
281-
MII_ANNPT = 7,
282-
MII_ANLPRNP = 8,
283-
MII_MSCR = 9,
284-
MII_MSSR = 10,
285-
MII_ESR = 15,
286275
MII_PHY_SCR = 16,
287276
};
277+
288278
/* PCS register */
289279
enum _pcs_reg {
290280
PCS_BMCR = 0,
@@ -297,102 +287,6 @@ enum _pcs_reg {
297287
PCS_ESR = 15,
298288
};
299289

300-
/* Basic Mode Control Register */
301-
enum _mii_bmcr {
302-
MII_BMCR_RESET = 0x8000,
303-
MII_BMCR_LOOP_BACK = 0x4000,
304-
MII_BMCR_SPEED_LSB = 0x2000,
305-
MII_BMCR_AN_ENABLE = 0x1000,
306-
MII_BMCR_POWER_DOWN = 0x0800,
307-
MII_BMCR_ISOLATE = 0x0400,
308-
MII_BMCR_RESTART_AN = 0x0200,
309-
MII_BMCR_DUPLEX_MODE = 0x0100,
310-
MII_BMCR_COL_TEST = 0x0080,
311-
MII_BMCR_SPEED_MSB = 0x0040,
312-
MII_BMCR_SPEED_RESERVED = 0x003f,
313-
MII_BMCR_SPEED_10 = 0,
314-
MII_BMCR_SPEED_100 = MII_BMCR_SPEED_LSB,
315-
MII_BMCR_SPEED_1000 = MII_BMCR_SPEED_MSB,
316-
};
317-
318-
/* Basic Mode Status Register */
319-
enum _mii_bmsr {
320-
MII_BMSR_100BT4 = 0x8000,
321-
MII_BMSR_100BX_FD = 0x4000,
322-
MII_BMSR_100BX_HD = 0x2000,
323-
MII_BMSR_10BT_FD = 0x1000,
324-
MII_BMSR_10BT_HD = 0x0800,
325-
MII_BMSR_100BT2_FD = 0x0400,
326-
MII_BMSR_100BT2_HD = 0x0200,
327-
MII_BMSR_EXT_STATUS = 0x0100,
328-
MII_BMSR_PREAMBLE_SUPP = 0x0040,
329-
MII_BMSR_AN_COMPLETE = 0x0020,
330-
MII_BMSR_REMOTE_FAULT = 0x0010,
331-
MII_BMSR_AN_ABILITY = 0x0008,
332-
MII_BMSR_LINK_STATUS = 0x0004,
333-
MII_BMSR_JABBER_DETECT = 0x0002,
334-
MII_BMSR_EXT_CAP = 0x0001,
335-
};
336-
337-
/* ANAR */
338-
enum _mii_anar {
339-
MII_ANAR_NEXT_PAGE = 0x8000,
340-
MII_ANAR_REMOTE_FAULT = 0x4000,
341-
MII_ANAR_ASYMMETRIC = 0x0800,
342-
MII_ANAR_PAUSE = 0x0400,
343-
MII_ANAR_100BT4 = 0x0200,
344-
MII_ANAR_100BX_FD = 0x0100,
345-
MII_ANAR_100BX_HD = 0x0080,
346-
MII_ANAR_10BT_FD = 0x0020,
347-
MII_ANAR_10BT_HD = 0x0010,
348-
MII_ANAR_SELECTOR = 0x001f,
349-
MII_IEEE8023_CSMACD = 0x0001,
350-
};
351-
352-
/* ANLPAR */
353-
enum _mii_anlpar {
354-
MII_ANLPAR_NEXT_PAGE = MII_ANAR_NEXT_PAGE,
355-
MII_ANLPAR_REMOTE_FAULT = MII_ANAR_REMOTE_FAULT,
356-
MII_ANLPAR_ASYMMETRIC = MII_ANAR_ASYMMETRIC,
357-
MII_ANLPAR_PAUSE = MII_ANAR_PAUSE,
358-
MII_ANLPAR_100BT4 = MII_ANAR_100BT4,
359-
MII_ANLPAR_100BX_FD = MII_ANAR_100BX_FD,
360-
MII_ANLPAR_100BX_HD = MII_ANAR_100BX_HD,
361-
MII_ANLPAR_10BT_FD = MII_ANAR_10BT_FD,
362-
MII_ANLPAR_10BT_HD = MII_ANAR_10BT_HD,
363-
MII_ANLPAR_SELECTOR = MII_ANAR_SELECTOR,
364-
};
365-
366-
/* Auto-Negotiation Expansion Register */
367-
enum _mii_aner {
368-
MII_ANER_PAR_DETECT_FAULT = 0x0010,
369-
MII_ANER_LP_NEXTPAGABLE = 0x0008,
370-
MII_ANER_NETXTPAGABLE = 0x0004,
371-
MII_ANER_PAGE_RECEIVED = 0x0002,
372-
MII_ANER_LP_NEGOTIABLE = 0x0001,
373-
};
374-
375-
/* MASTER-SLAVE Control Register */
376-
enum _mii_mscr {
377-
MII_MSCR_TEST_MODE = 0xe000,
378-
MII_MSCR_CFG_ENABLE = 0x1000,
379-
MII_MSCR_CFG_VALUE = 0x0800,
380-
MII_MSCR_PORT_VALUE = 0x0400,
381-
MII_MSCR_1000BT_FD = 0x0200,
382-
MII_MSCR_1000BT_HD = 0X0100,
383-
};
384-
385-
/* MASTER-SLAVE Status Register */
386-
enum _mii_mssr {
387-
MII_MSSR_CFG_FAULT = 0x8000,
388-
MII_MSSR_CFG_RES = 0x4000,
389-
MII_MSSR_LOCAL_RCV_STATUS = 0x2000,
390-
MII_MSSR_REMOTE_RCVR = 0x1000,
391-
MII_MSSR_LP_1000BT_FD = 0x0800,
392-
MII_MSSR_LP_1000BT_HD = 0x0400,
393-
MII_MSSR_IDLE_ERR_COUNT = 0x00ff,
394-
};
395-
396290
/* IEEE Extened Status Register */
397291
enum _mii_esr {
398292
MII_ESR_1000BX_FD = 0x8000,

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