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Merge tag 'usb-for-v4.6' of http://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb into usb-next
Felipe writes: usb changes for v4.6 merge window This is almost all under drivers/usb/dwc2/. Many changes to the host side implementation of dwc2 have been done by Douglas Anderson. We also have USB 3.1 support added to the Gadget Framework and, because of that work, dwc3 got support to Synopsys new DWC_usb31 IP core. Other than these 2 important series, we also have the usual collection of non-critical fixes, Documentation updates, and minor changes all over the place.
2 parents 83253b3 + 0561f77 commit 3d0712d

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‎Documentation/devicetree/bindings/usb/dwc2.txt

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,8 @@ Required properties:
88
- rockchip,rk3066-usb: The DWC2 USB controller instance in the rk3066 Soc;
99
- "rockchip,rk3188-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3188 Soc;
1010
- "rockchip,rk3288-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3288 Soc;
11+
- "lantiq,arx100-usb": The DWC2 USB controller instance in Lantiq ARX SoCs;
12+
- "lantiq,xrx200-usb": The DWC2 USB controller instance in Lantiq XRX SoCs;
1113
- snps,dwc2: A generic DWC2 USB controller with default parameters.
1214
- reg : Should contain 1 register range (address and length)
1315
- interrupts : Should contain 1 interrupt

‎Documentation/usb/chipidea.txt

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -26,16 +26,17 @@ cat /sys/kernel/debug/ci_hdrc.0/registers
2626
On B-device:
2727
echo 1 > /sys/bus/platform/devices/ci_hdrc.0/inputs/b_bus_req
2828

29-
if HNP polling is not supported, also need:
30-
On A-device:
31-
echo 0 > /sys/bus/platform/devices/ci_hdrc.0/inputs/a_bus_req
32-
3329
B-device should take host role and enumrate A-device.
3430

3531
4) A-device switch back to host.
3632
On B-device:
3733
echo 0 > /sys/bus/platform/devices/ci_hdrc.0/inputs/b_bus_req
3834

35+
or, by introducing HNP polling, B-Host can know when A-peripheral wish
36+
to be host role, so this role switch also can be trigged in A-peripheral
37+
side by answering the polling from B-Host, this can be done on A-device:
38+
echo 1 > /sys/bus/platform/devices/ci_hdrc.0/inputs/a_bus_req
39+
3940
A-device should switch back to host and enumrate B-device.
4041

4142
5) Remove B-device(unplug micro B plug) and insert again in 10 seconds,

‎arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h

Lines changed: 0 additions & 198 deletions
Original file line numberDiff line numberDiff line change
@@ -395,204 +395,6 @@
395395
#define CRP_AD_CBE_BESL 20
396396
#define CRP_AD_CBE_WRITE 0x00010000
397397

398-
399-
/*
400-
* USB Device Controller
401-
*
402-
* These are used by the USB gadget driver, so they don't follow the
403-
* IXP4XX_ naming convetions.
404-
*
405-
*/
406-
# define IXP4XX_USB_REG(x) (*((volatile u32 *)(x)))
407-
408-
/* UDC Undocumented - Reserved1 */
409-
#define UDC_RES1 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0004)
410-
/* UDC Undocumented - Reserved2 */
411-
#define UDC_RES2 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0008)
412-
/* UDC Undocumented - Reserved3 */
413-
#define UDC_RES3 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x000C)
414-
/* UDC Control Register */
415-
#define UDCCR IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0000)
416-
/* UDC Endpoint 0 Control/Status Register */
417-
#define UDCCS0 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0010)
418-
/* UDC Endpoint 1 (IN) Control/Status Register */
419-
#define UDCCS1 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0014)
420-
/* UDC Endpoint 2 (OUT) Control/Status Register */
421-
#define UDCCS2 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0018)
422-
/* UDC Endpoint 3 (IN) Control/Status Register */
423-
#define UDCCS3 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x001C)
424-
/* UDC Endpoint 4 (OUT) Control/Status Register */
425-
#define UDCCS4 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0020)
426-
/* UDC Endpoint 5 (Interrupt) Control/Status Register */
427-
#define UDCCS5 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0024)
428-
/* UDC Endpoint 6 (IN) Control/Status Register */
429-
#define UDCCS6 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0028)
430-
/* UDC Endpoint 7 (OUT) Control/Status Register */
431-
#define UDCCS7 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x002C)
432-
/* UDC Endpoint 8 (IN) Control/Status Register */
433-
#define UDCCS8 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0030)
434-
/* UDC Endpoint 9 (OUT) Control/Status Register */
435-
#define UDCCS9 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0034)
436-
/* UDC Endpoint 10 (Interrupt) Control/Status Register */
437-
#define UDCCS10 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0038)
438-
/* UDC Endpoint 11 (IN) Control/Status Register */
439-
#define UDCCS11 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x003C)
440-
/* UDC Endpoint 12 (OUT) Control/Status Register */
441-
#define UDCCS12 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0040)
442-
/* UDC Endpoint 13 (IN) Control/Status Register */
443-
#define UDCCS13 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0044)
444-
/* UDC Endpoint 14 (OUT) Control/Status Register */
445-
#define UDCCS14 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0048)
446-
/* UDC Endpoint 15 (Interrupt) Control/Status Register */
447-
#define UDCCS15 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x004C)
448-
/* UDC Frame Number Register High */
449-
#define UFNRH IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0060)
450-
/* UDC Frame Number Register Low */
451-
#define UFNRL IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0064)
452-
/* UDC Byte Count Reg 2 */
453-
#define UBCR2 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0068)
454-
/* UDC Byte Count Reg 4 */
455-
#define UBCR4 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x006c)
456-
/* UDC Byte Count Reg 7 */
457-
#define UBCR7 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0070)
458-
/* UDC Byte Count Reg 9 */
459-
#define UBCR9 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0074)
460-
/* UDC Byte Count Reg 12 */
461-
#define UBCR12 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0078)
462-
/* UDC Byte Count Reg 14 */
463-
#define UBCR14 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x007c)
464-
/* UDC Endpoint 0 Data Register */
465-
#define UDDR0 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0080)
466-
/* UDC Endpoint 1 Data Register */
467-
#define UDDR1 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0100)
468-
/* UDC Endpoint 2 Data Register */
469-
#define UDDR2 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0180)
470-
/* UDC Endpoint 3 Data Register */
471-
#define UDDR3 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0200)
472-
/* UDC Endpoint 4 Data Register */
473-
#define UDDR4 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0400)
474-
/* UDC Endpoint 5 Data Register */
475-
#define UDDR5 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x00A0)
476-
/* UDC Endpoint 6 Data Register */
477-
#define UDDR6 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0600)
478-
/* UDC Endpoint 7 Data Register */
479-
#define UDDR7 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0680)
480-
/* UDC Endpoint 8 Data Register */
481-
#define UDDR8 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0700)
482-
/* UDC Endpoint 9 Data Register */
483-
#define UDDR9 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0900)
484-
/* UDC Endpoint 10 Data Register */
485-
#define UDDR10 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x00C0)
486-
/* UDC Endpoint 11 Data Register */
487-
#define UDDR11 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0B00)
488-
/* UDC Endpoint 12 Data Register */
489-
#define UDDR12 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0B80)
490-
/* UDC Endpoint 13 Data Register */
491-
#define UDDR13 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0C00)
492-
/* UDC Endpoint 14 Data Register */
493-
#define UDDR14 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0E00)
494-
/* UDC Endpoint 15 Data Register */
495-
#define UDDR15 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x00E0)
496-
/* UDC Interrupt Control Register 0 */
497-
#define UICR0 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0050)
498-
/* UDC Interrupt Control Register 1 */
499-
#define UICR1 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0054)
500-
/* UDC Status Interrupt Register 0 */
501-
#define USIR0 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0058)
502-
/* UDC Status Interrupt Register 1 */
503-
#define USIR1 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x005C)
504-
505-
#define UDCCR_UDE (1 << 0) /* UDC enable */
506-
#define UDCCR_UDA (1 << 1) /* UDC active */
507-
#define UDCCR_RSM (1 << 2) /* Device resume */
508-
#define UDCCR_RESIR (1 << 3) /* Resume interrupt request */
509-
#define UDCCR_SUSIR (1 << 4) /* Suspend interrupt request */
510-
#define UDCCR_SRM (1 << 5) /* Suspend/resume interrupt mask */
511-
#define UDCCR_RSTIR (1 << 6) /* Reset interrupt request */
512-
#define UDCCR_REM (1 << 7) /* Reset interrupt mask */
513-
514-
#define UDCCS0_OPR (1 << 0) /* OUT packet ready */
515-
#define UDCCS0_IPR (1 << 1) /* IN packet ready */
516-
#define UDCCS0_FTF (1 << 2) /* Flush Tx FIFO */
517-
#define UDCCS0_DRWF (1 << 3) /* Device remote wakeup feature */
518-
#define UDCCS0_SST (1 << 4) /* Sent stall */
519-
#define UDCCS0_FST (1 << 5) /* Force stall */
520-
#define UDCCS0_RNE (1 << 6) /* Receive FIFO no empty */
521-
#define UDCCS0_SA (1 << 7) /* Setup active */
522-
523-
#define UDCCS_BI_TFS (1 << 0) /* Transmit FIFO service */
524-
#define UDCCS_BI_TPC (1 << 1) /* Transmit packet complete */
525-
#define UDCCS_BI_FTF (1 << 2) /* Flush Tx FIFO */
526-
#define UDCCS_BI_TUR (1 << 3) /* Transmit FIFO underrun */
527-
#define UDCCS_BI_SST (1 << 4) /* Sent stall */
528-
#define UDCCS_BI_FST (1 << 5) /* Force stall */
529-
#define UDCCS_BI_TSP (1 << 7) /* Transmit short packet */
530-
531-
#define UDCCS_BO_RFS (1 << 0) /* Receive FIFO service */
532-
#define UDCCS_BO_RPC (1 << 1) /* Receive packet complete */
533-
#define UDCCS_BO_DME (1 << 3) /* DMA enable */
534-
#define UDCCS_BO_SST (1 << 4) /* Sent stall */
535-
#define UDCCS_BO_FST (1 << 5) /* Force stall */
536-
#define UDCCS_BO_RNE (1 << 6) /* Receive FIFO not empty */
537-
#define UDCCS_BO_RSP (1 << 7) /* Receive short packet */
538-
539-
#define UDCCS_II_TFS (1 << 0) /* Transmit FIFO service */
540-
#define UDCCS_II_TPC (1 << 1) /* Transmit packet complete */
541-
#define UDCCS_II_FTF (1 << 2) /* Flush Tx FIFO */
542-
#define UDCCS_II_TUR (1 << 3) /* Transmit FIFO underrun */
543-
#define UDCCS_II_TSP (1 << 7) /* Transmit short packet */
544-
545-
#define UDCCS_IO_RFS (1 << 0) /* Receive FIFO service */
546-
#define UDCCS_IO_RPC (1 << 1) /* Receive packet complete */
547-
#define UDCCS_IO_ROF (1 << 3) /* Receive overflow */
548-
#define UDCCS_IO_DME (1 << 3) /* DMA enable */
549-
#define UDCCS_IO_RNE (1 << 6) /* Receive FIFO not empty */
550-
#define UDCCS_IO_RSP (1 << 7) /* Receive short packet */
551-
552-
#define UDCCS_INT_TFS (1 << 0) /* Transmit FIFO service */
553-
#define UDCCS_INT_TPC (1 << 1) /* Transmit packet complete */
554-
#define UDCCS_INT_FTF (1 << 2) /* Flush Tx FIFO */
555-
#define UDCCS_INT_TUR (1 << 3) /* Transmit FIFO underrun */
556-
#define UDCCS_INT_SST (1 << 4) /* Sent stall */
557-
#define UDCCS_INT_FST (1 << 5) /* Force stall */
558-
#define UDCCS_INT_TSP (1 << 7) /* Transmit short packet */
559-
560-
#define UICR0_IM0 (1 << 0) /* Interrupt mask ep 0 */
561-
#define UICR0_IM1 (1 << 1) /* Interrupt mask ep 1 */
562-
#define UICR0_IM2 (1 << 2) /* Interrupt mask ep 2 */
563-
#define UICR0_IM3 (1 << 3) /* Interrupt mask ep 3 */
564-
#define UICR0_IM4 (1 << 4) /* Interrupt mask ep 4 */
565-
#define UICR0_IM5 (1 << 5) /* Interrupt mask ep 5 */
566-
#define UICR0_IM6 (1 << 6) /* Interrupt mask ep 6 */
567-
#define UICR0_IM7 (1 << 7) /* Interrupt mask ep 7 */
568-
569-
#define UICR1_IM8 (1 << 0) /* Interrupt mask ep 8 */
570-
#define UICR1_IM9 (1 << 1) /* Interrupt mask ep 9 */
571-
#define UICR1_IM10 (1 << 2) /* Interrupt mask ep 10 */
572-
#define UICR1_IM11 (1 << 3) /* Interrupt mask ep 11 */
573-
#define UICR1_IM12 (1 << 4) /* Interrupt mask ep 12 */
574-
#define UICR1_IM13 (1 << 5) /* Interrupt mask ep 13 */
575-
#define UICR1_IM14 (1 << 6) /* Interrupt mask ep 14 */
576-
#define UICR1_IM15 (1 << 7) /* Interrupt mask ep 15 */
577-
578-
#define USIR0_IR0 (1 << 0) /* Interrupt request ep 0 */
579-
#define USIR0_IR1 (1 << 1) /* Interrupt request ep 1 */
580-
#define USIR0_IR2 (1 << 2) /* Interrupt request ep 2 */
581-
#define USIR0_IR3 (1 << 3) /* Interrupt request ep 3 */
582-
#define USIR0_IR4 (1 << 4) /* Interrupt request ep 4 */
583-
#define USIR0_IR5 (1 << 5) /* Interrupt request ep 5 */
584-
#define USIR0_IR6 (1 << 6) /* Interrupt request ep 6 */
585-
#define USIR0_IR7 (1 << 7) /* Interrupt request ep 7 */
586-
587-
#define USIR1_IR8 (1 << 0) /* Interrupt request ep 8 */
588-
#define USIR1_IR9 (1 << 1) /* Interrupt request ep 9 */
589-
#define USIR1_IR10 (1 << 2) /* Interrupt request ep 10 */
590-
#define USIR1_IR11 (1 << 3) /* Interrupt request ep 11 */
591-
#define USIR1_IR12 (1 << 4) /* Interrupt request ep 12 */
592-
#define USIR1_IR13 (1 << 5) /* Interrupt request ep 13 */
593-
#define USIR1_IR14 (1 << 6) /* Interrupt request ep 14 */
594-
#define USIR1_IR15 (1 << 7) /* Interrupt request ep 15 */
595-
596398
#define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
597399

598400
/* "fuse" bits of IXP_EXP_CFG2 */

‎arch/arm/mach-pxa/include/mach/pxa25x-udc.h

Lines changed: 0 additions & 163 deletions
Original file line numberDiff line numberDiff line change
@@ -1,163 +0,0 @@
1-
#ifndef _ASM_ARCH_PXA25X_UDC_H
2-
#define _ASM_ARCH_PXA25X_UDC_H
3-
4-
#ifdef _ASM_ARCH_PXA27X_UDC_H
5-
#error "You can't include both PXA25x and PXA27x UDC support"
6-
#endif
7-
8-
#define UDC_RES1 __REG(0x40600004) /* UDC Undocumented - Reserved1 */
9-
#define UDC_RES2 __REG(0x40600008) /* UDC Undocumented - Reserved2 */
10-
#define UDC_RES3 __REG(0x4060000C) /* UDC Undocumented - Reserved3 */
11-
12-
#define UDCCR __REG(0x40600000) /* UDC Control Register */
13-
#define UDCCR_UDE (1 << 0) /* UDC enable */
14-
#define UDCCR_UDA (1 << 1) /* UDC active */
15-
#define UDCCR_RSM (1 << 2) /* Device resume */
16-
#define UDCCR_RESIR (1 << 3) /* Resume interrupt request */
17-
#define UDCCR_SUSIR (1 << 4) /* Suspend interrupt request */
18-
#define UDCCR_SRM (1 << 5) /* Suspend/resume interrupt mask */
19-
#define UDCCR_RSTIR (1 << 6) /* Reset interrupt request */
20-
#define UDCCR_REM (1 << 7) /* Reset interrupt mask */
21-
22-
#define UDCCS0 __REG(0x40600010) /* UDC Endpoint 0 Control/Status Register */
23-
#define UDCCS0_OPR (1 << 0) /* OUT packet ready */
24-
#define UDCCS0_IPR (1 << 1) /* IN packet ready */
25-
#define UDCCS0_FTF (1 << 2) /* Flush Tx FIFO */
26-
#define UDCCS0_DRWF (1 << 3) /* Device remote wakeup feature */
27-
#define UDCCS0_SST (1 << 4) /* Sent stall */
28-
#define UDCCS0_FST (1 << 5) /* Force stall */
29-
#define UDCCS0_RNE (1 << 6) /* Receive FIFO no empty */
30-
#define UDCCS0_SA (1 << 7) /* Setup active */
31-
32-
/* Bulk IN - Endpoint 1,6,11 */
33-
#define UDCCS1 __REG(0x40600014) /* UDC Endpoint 1 (IN) Control/Status Register */
34-
#define UDCCS6 __REG(0x40600028) /* UDC Endpoint 6 (IN) Control/Status Register */
35-
#define UDCCS11 __REG(0x4060003C) /* UDC Endpoint 11 (IN) Control/Status Register */
36-
37-
#define UDCCS_BI_TFS (1 << 0) /* Transmit FIFO service */
38-
#define UDCCS_BI_TPC (1 << 1) /* Transmit packet complete */
39-
#define UDCCS_BI_FTF (1 << 2) /* Flush Tx FIFO */
40-
#define UDCCS_BI_TUR (1 << 3) /* Transmit FIFO underrun */
41-
#define UDCCS_BI_SST (1 << 4) /* Sent stall */
42-
#define UDCCS_BI_FST (1 << 5) /* Force stall */
43-
#define UDCCS_BI_TSP (1 << 7) /* Transmit short packet */
44-
45-
/* Bulk OUT - Endpoint 2,7,12 */
46-
#define UDCCS2 __REG(0x40600018) /* UDC Endpoint 2 (OUT) Control/Status Register */
47-
#define UDCCS7 __REG(0x4060002C) /* UDC Endpoint 7 (OUT) Control/Status Register */
48-
#define UDCCS12 __REG(0x40600040) /* UDC Endpoint 12 (OUT) Control/Status Register */
49-
50-
#define UDCCS_BO_RFS (1 << 0) /* Receive FIFO service */
51-
#define UDCCS_BO_RPC (1 << 1) /* Receive packet complete */
52-
#define UDCCS_BO_DME (1 << 3) /* DMA enable */
53-
#define UDCCS_BO_SST (1 << 4) /* Sent stall */
54-
#define UDCCS_BO_FST (1 << 5) /* Force stall */
55-
#define UDCCS_BO_RNE (1 << 6) /* Receive FIFO not empty */
56-
#define UDCCS_BO_RSP (1 << 7) /* Receive short packet */
57-
58-
/* Isochronous IN - Endpoint 3,8,13 */
59-
#define UDCCS3 __REG(0x4060001C) /* UDC Endpoint 3 (IN) Control/Status Register */
60-
#define UDCCS8 __REG(0x40600030) /* UDC Endpoint 8 (IN) Control/Status Register */
61-
#define UDCCS13 __REG(0x40600044) /* UDC Endpoint 13 (IN) Control/Status Register */
62-
63-
#define UDCCS_II_TFS (1 << 0) /* Transmit FIFO service */
64-
#define UDCCS_II_TPC (1 << 1) /* Transmit packet complete */
65-
#define UDCCS_II_FTF (1 << 2) /* Flush Tx FIFO */
66-
#define UDCCS_II_TUR (1 << 3) /* Transmit FIFO underrun */
67-
#define UDCCS_II_TSP (1 << 7) /* Transmit short packet */
68-
69-
/* Isochronous OUT - Endpoint 4,9,14 */
70-
#define UDCCS4 __REG(0x40600020) /* UDC Endpoint 4 (OUT) Control/Status Register */
71-
#define UDCCS9 __REG(0x40600034) /* UDC Endpoint 9 (OUT) Control/Status Register */
72-
#define UDCCS14 __REG(0x40600048) /* UDC Endpoint 14 (OUT) Control/Status Register */
73-
74-
#define UDCCS_IO_RFS (1 << 0) /* Receive FIFO service */
75-
#define UDCCS_IO_RPC (1 << 1) /* Receive packet complete */
76-
#define UDCCS_IO_ROF (1 << 2) /* Receive overflow */
77-
#define UDCCS_IO_DME (1 << 3) /* DMA enable */
78-
#define UDCCS_IO_RNE (1 << 6) /* Receive FIFO not empty */
79-
#define UDCCS_IO_RSP (1 << 7) /* Receive short packet */
80-
81-
/* Interrupt IN - Endpoint 5,10,15 */
82-
#define UDCCS5 __REG(0x40600024) /* UDC Endpoint 5 (Interrupt) Control/Status Register */
83-
#define UDCCS10 __REG(0x40600038) /* UDC Endpoint 10 (Interrupt) Control/Status Register */
84-
#define UDCCS15 __REG(0x4060004C) /* UDC Endpoint 15 (Interrupt) Control/Status Register */
85-
86-
#define UDCCS_INT_TFS (1 << 0) /* Transmit FIFO service */
87-
#define UDCCS_INT_TPC (1 << 1) /* Transmit packet complete */
88-
#define UDCCS_INT_FTF (1 << 2) /* Flush Tx FIFO */
89-
#define UDCCS_INT_TUR (1 << 3) /* Transmit FIFO underrun */
90-
#define UDCCS_INT_SST (1 << 4) /* Sent stall */
91-
#define UDCCS_INT_FST (1 << 5) /* Force stall */
92-
#define UDCCS_INT_TSP (1 << 7) /* Transmit short packet */
93-
94-
#define UFNRH __REG(0x40600060) /* UDC Frame Number Register High */
95-
#define UFNRL __REG(0x40600064) /* UDC Frame Number Register Low */
96-
#define UBCR2 __REG(0x40600068) /* UDC Byte Count Reg 2 */
97-
#define UBCR4 __REG(0x4060006c) /* UDC Byte Count Reg 4 */
98-
#define UBCR7 __REG(0x40600070) /* UDC Byte Count Reg 7 */
99-
#define UBCR9 __REG(0x40600074) /* UDC Byte Count Reg 9 */
100-
#define UBCR12 __REG(0x40600078) /* UDC Byte Count Reg 12 */
101-
#define UBCR14 __REG(0x4060007c) /* UDC Byte Count Reg 14 */
102-
#define UDDR0 __REG(0x40600080) /* UDC Endpoint 0 Data Register */
103-
#define UDDR1 __REG(0x40600100) /* UDC Endpoint 1 Data Register */
104-
#define UDDR2 __REG(0x40600180) /* UDC Endpoint 2 Data Register */
105-
#define UDDR3 __REG(0x40600200) /* UDC Endpoint 3 Data Register */
106-
#define UDDR4 __REG(0x40600400) /* UDC Endpoint 4 Data Register */
107-
#define UDDR5 __REG(0x406000A0) /* UDC Endpoint 5 Data Register */
108-
#define UDDR6 __REG(0x40600600) /* UDC Endpoint 6 Data Register */
109-
#define UDDR7 __REG(0x40600680) /* UDC Endpoint 7 Data Register */
110-
#define UDDR8 __REG(0x40600700) /* UDC Endpoint 8 Data Register */
111-
#define UDDR9 __REG(0x40600900) /* UDC Endpoint 9 Data Register */
112-
#define UDDR10 __REG(0x406000C0) /* UDC Endpoint 10 Data Register */
113-
#define UDDR11 __REG(0x40600B00) /* UDC Endpoint 11 Data Register */
114-
#define UDDR12 __REG(0x40600B80) /* UDC Endpoint 12 Data Register */
115-
#define UDDR13 __REG(0x40600C00) /* UDC Endpoint 13 Data Register */
116-
#define UDDR14 __REG(0x40600E00) /* UDC Endpoint 14 Data Register */
117-
#define UDDR15 __REG(0x406000E0) /* UDC Endpoint 15 Data Register */
118-
119-
#define UICR0 __REG(0x40600050) /* UDC Interrupt Control Register 0 */
120-
121-
#define UICR0_IM0 (1 << 0) /* Interrupt mask ep 0 */
122-
#define UICR0_IM1 (1 << 1) /* Interrupt mask ep 1 */
123-
#define UICR0_IM2 (1 << 2) /* Interrupt mask ep 2 */
124-
#define UICR0_IM3 (1 << 3) /* Interrupt mask ep 3 */
125-
#define UICR0_IM4 (1 << 4) /* Interrupt mask ep 4 */
126-
#define UICR0_IM5 (1 << 5) /* Interrupt mask ep 5 */
127-
#define UICR0_IM6 (1 << 6) /* Interrupt mask ep 6 */
128-
#define UICR0_IM7 (1 << 7) /* Interrupt mask ep 7 */
129-
130-
#define UICR1 __REG(0x40600054) /* UDC Interrupt Control Register 1 */
131-
132-
#define UICR1_IM8 (1 << 0) /* Interrupt mask ep 8 */
133-
#define UICR1_IM9 (1 << 1) /* Interrupt mask ep 9 */
134-
#define UICR1_IM10 (1 << 2) /* Interrupt mask ep 10 */
135-
#define UICR1_IM11 (1 << 3) /* Interrupt mask ep 11 */
136-
#define UICR1_IM12 (1 << 4) /* Interrupt mask ep 12 */
137-
#define UICR1_IM13 (1 << 5) /* Interrupt mask ep 13 */
138-
#define UICR1_IM14 (1 << 6) /* Interrupt mask ep 14 */
139-
#define UICR1_IM15 (1 << 7) /* Interrupt mask ep 15 */
140-
141-
#define USIR0 __REG(0x40600058) /* UDC Status Interrupt Register 0 */
142-
143-
#define USIR0_IR0 (1 << 0) /* Interrupt request ep 0 */
144-
#define USIR0_IR1 (1 << 1) /* Interrupt request ep 1 */
145-
#define USIR0_IR2 (1 << 2) /* Interrupt request ep 2 */
146-
#define USIR0_IR3 (1 << 3) /* Interrupt request ep 3 */
147-
#define USIR0_IR4 (1 << 4) /* Interrupt request ep 4 */
148-
#define USIR0_IR5 (1 << 5) /* Interrupt request ep 5 */
149-
#define USIR0_IR6 (1 << 6) /* Interrupt request ep 6 */
150-
#define USIR0_IR7 (1 << 7) /* Interrupt request ep 7 */
151-
152-
#define USIR1 __REG(0x4060005C) /* UDC Status Interrupt Register 1 */
153-
154-
#define USIR1_IR8 (1 << 0) /* Interrupt request ep 8 */
155-
#define USIR1_IR9 (1 << 1) /* Interrupt request ep 9 */
156-
#define USIR1_IR10 (1 << 2) /* Interrupt request ep 10 */
157-
#define USIR1_IR11 (1 << 3) /* Interrupt request ep 11 */
158-
#define USIR1_IR12 (1 << 4) /* Interrupt request ep 12 */
159-
#define USIR1_IR13 (1 << 5) /* Interrupt request ep 13 */
160-
#define USIR1_IR14 (1 << 6) /* Interrupt request ep 14 */
161-
#define USIR1_IR15 (1 << 7) /* Interrupt request ep 15 */
162-
163-
#endif

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