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Jolly ShahMichal Simek
Jolly Shah
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Michal Simek
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drivers: clk: Add ZynqMP clock driver
This patch adds CCF compliant clock driver for ZynqMP. Clock driver queries supported clock information from firmware and regiters pll and output clocks with CCF. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Tejas Patel <tejasp@xilinx.com> Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Acked-by: Olof Johansson <olof@lixom.net> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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‎drivers/clk/Kconfig

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@@ -299,5 +299,6 @@ source "drivers/clk/sunxi-ng/Kconfig"
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source "drivers/clk/tegra/Kconfig"
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source "drivers/clk/ti/Kconfig"
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source "drivers/clk/uniphier/Kconfig"
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source "drivers/clk/zynqmp/Kconfig"
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endmenu

‎drivers/clk/Makefile

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@@ -108,3 +108,4 @@ obj-$(CONFIG_X86) += x86/
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endif
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obj-$(CONFIG_ARCH_ZX) += zte/
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obj-$(CONFIG_ARCH_ZYNQ) += zynq/
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obj-$(CONFIG_COMMON_CLK_ZYNQMP) += zynqmp/

‎drivers/clk/zynqmp/Kconfig

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# SPDX-License-Identifier: GPL-2.0
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config COMMON_CLK_ZYNQMP
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bool "Support for Xilinx ZynqMP Ultrascale+ clock controllers"
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depends on ARCH_ZYNQMP || COMPILE_TEST
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depends on ZYNQMP_FIRMWARE
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help
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Support for the Zynqmp Ultrascale clock controller.
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It has a dependency on the PMU firmware.
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Say Y if you want to include clock support.

‎drivers/clk/zynqmp/Makefile

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# SPDX-License-Identifier: GPL-2.0
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# Zynq Ultrascale+ MPSoC clock specific Makefile
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obj-$(CONFIG_ARCH_ZYNQMP) += pll.o clk-gate-zynqmp.o divider.o clk-mux-zynqmp.o clkc.o

‎drivers/clk/zynqmp/clk-gate-zynqmp.c

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// SPDX-License-Identifier: GPL-2.0
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/*
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* Zynq UltraScale+ MPSoC clock controller
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*
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* Copyright (C) 2016-2018 Xilinx
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*
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* Gated clock implementation
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*/
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#include <linux/clk-provider.h>
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#include <linux/slab.h>
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#include "clk-zynqmp.h"
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/**
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* struct clk_gate - gating clock
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* @hw: handle between common and hardware-specific interfaces
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* @flags: hardware-specific flags
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* @clk_id: Id of clock
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*/
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struct zynqmp_clk_gate {
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struct clk_hw hw;
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u8 flags;
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u32 clk_id;
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};
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#define to_zynqmp_clk_gate(_hw) container_of(_hw, struct zynqmp_clk_gate, hw)
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/**
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* zynqmp_clk_gate_enable() - Enable clock
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* @hw: handle between common and hardware-specific interfaces
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*
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* Return: 0 on success else error code
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*/
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static int zynqmp_clk_gate_enable(struct clk_hw *hw)
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{
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struct zynqmp_clk_gate *gate = to_zynqmp_clk_gate(hw);
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const char *clk_name = clk_hw_get_name(hw);
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u32 clk_id = gate->clk_id;
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int ret;
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const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
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ret = eemi_ops->clock_enable(clk_id);
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if (ret)
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pr_warn_once("%s() clock enabled failed for %s, ret = %d\n",
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__func__, clk_name, ret);
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return ret;
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}
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/*
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* zynqmp_clk_gate_disable() - Disable clock
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* @hw: handle between common and hardware-specific interfaces
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*/
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static void zynqmp_clk_gate_disable(struct clk_hw *hw)
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{
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struct zynqmp_clk_gate *gate = to_zynqmp_clk_gate(hw);
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const char *clk_name = clk_hw_get_name(hw);
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u32 clk_id = gate->clk_id;
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int ret;
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const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
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ret = eemi_ops->clock_disable(clk_id);
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if (ret)
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pr_warn_once("%s() clock disable failed for %s, ret = %d\n",
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__func__, clk_name, ret);
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}
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/**
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* zynqmp_clk_gate_is_enable() - Check clock state
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* @hw: handle between common and hardware-specific interfaces
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*
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* Return: 1 if enabled, 0 if disabled else error code
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*/
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static int zynqmp_clk_gate_is_enabled(struct clk_hw *hw)
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{
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struct zynqmp_clk_gate *gate = to_zynqmp_clk_gate(hw);
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const char *clk_name = clk_hw_get_name(hw);
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u32 clk_id = gate->clk_id;
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int state, ret;
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const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
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ret = eemi_ops->clock_getstate(clk_id, &state);
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if (ret) {
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pr_warn_once("%s() clock get state failed for %s, ret = %d\n",
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__func__, clk_name, ret);
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return -EIO;
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}
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return state ? 1 : 0;
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}
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static const struct clk_ops zynqmp_clk_gate_ops = {
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.enable = zynqmp_clk_gate_enable,
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.disable = zynqmp_clk_gate_disable,
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.is_enabled = zynqmp_clk_gate_is_enabled,
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};
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/**
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* zynqmp_clk_register_gate() - Register a gate clock with the clock framework
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* @name: Name of this clock
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* @clk_id: Id of this clock
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* @parents: Name of this clock's parents
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* @num_parents: Number of parents
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* @nodes: Clock topology node
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*
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* Return: clock hardware of the registered clock gate
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*/
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struct clk_hw *zynqmp_clk_register_gate(const char *name, u32 clk_id,
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const char * const *parents,
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u8 num_parents,
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const struct clock_topology *nodes)
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{
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struct zynqmp_clk_gate *gate;
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struct clk_hw *hw;
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int ret;
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struct clk_init_data init;
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/* allocate the gate */
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gate = kzalloc(sizeof(*gate), GFP_KERNEL);
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if (!gate)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &zynqmp_clk_gate_ops;
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init.flags = nodes->flag;
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init.parent_names = parents;
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init.num_parents = 1;
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/* struct clk_gate assignments */
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gate->flags = nodes->type_flag;
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gate->hw.init = &init;
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gate->clk_id = clk_id;
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hw = &gate->hw;
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ret = clk_hw_register(NULL, hw);
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if (ret) {
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kfree(gate);
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hw = ERR_PTR(ret);
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}
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return hw;
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}

‎drivers/clk/zynqmp/clk-mux-zynqmp.c

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// SPDX-License-Identifier: GPL-2.0
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/*
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* Zynq UltraScale+ MPSoC mux
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*
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* Copyright (C) 2016-2018 Xilinx
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*/
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#include <linux/clk-provider.h>
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#include <linux/slab.h>
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#include "clk-zynqmp.h"
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/*
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* DOC: basic adjustable multiplexer clock that cannot gate
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*
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* Traits of this clock:
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* prepare - clk_prepare only ensures that parents are prepared
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* enable - clk_enable only ensures that parents are enabled
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* rate - rate is only affected by parent switching. No clk_set_rate support
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* parent - parent is adjustable through clk_set_parent
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*/
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/**
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* struct zynqmp_clk_mux - multiplexer clock
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*
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* @hw: handle between common and hardware-specific interfaces
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* @flags: hardware-specific flags
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* @clk_id: Id of clock
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*/
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struct zynqmp_clk_mux {
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struct clk_hw hw;
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u8 flags;
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u32 clk_id;
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};
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#define to_zynqmp_clk_mux(_hw) container_of(_hw, struct zynqmp_clk_mux, hw)
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/**
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* zynqmp_clk_mux_get_parent() - Get parent of clock
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* @hw: handle between common and hardware-specific interfaces
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*
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* Return: Parent index
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*/
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static u8 zynqmp_clk_mux_get_parent(struct clk_hw *hw)
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{
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struct zynqmp_clk_mux *mux = to_zynqmp_clk_mux(hw);
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const char *clk_name = clk_hw_get_name(hw);
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u32 clk_id = mux->clk_id;
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u32 val;
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int ret;
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const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
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ret = eemi_ops->clock_getparent(clk_id, &val);
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if (ret)
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pr_warn_once("%s() getparent failed for clock: %s, ret = %d\n",
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__func__, clk_name, ret);
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return val;
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}
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/**
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* zynqmp_clk_mux_set_parent() - Set parent of clock
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* @hw: handle between common and hardware-specific interfaces
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* @index: Parent index
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*
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* Return: 0 on success else error+reason
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*/
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static int zynqmp_clk_mux_set_parent(struct clk_hw *hw, u8 index)
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{
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struct zynqmp_clk_mux *mux = to_zynqmp_clk_mux(hw);
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const char *clk_name = clk_hw_get_name(hw);
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u32 clk_id = mux->clk_id;
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int ret;
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const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
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ret = eemi_ops->clock_setparent(clk_id, index);
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if (ret)
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pr_warn_once("%s() set parent failed for clock: %s, ret = %d\n",
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__func__, clk_name, ret);
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return ret;
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}
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static const struct clk_ops zynqmp_clk_mux_ops = {
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.get_parent = zynqmp_clk_mux_get_parent,
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.set_parent = zynqmp_clk_mux_set_parent,
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.determine_rate = __clk_mux_determine_rate,
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};
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static const struct clk_ops zynqmp_clk_mux_ro_ops = {
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.get_parent = zynqmp_clk_mux_get_parent,
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};
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/**
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* zynqmp_clk_register_mux() - Register a mux table with the clock
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* framework
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* @name: Name of this clock
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* @clk_id: Id of this clock
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* @parents: Name of this clock's parents
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* @num_parents: Number of parents
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* @nodes: Clock topology node
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*
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* Return: clock hardware of the registered clock mux
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*/
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struct clk_hw *zynqmp_clk_register_mux(const char *name, u32 clk_id,
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const char * const *parents,
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u8 num_parents,
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const struct clock_topology *nodes)
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{
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struct zynqmp_clk_mux *mux;
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struct clk_hw *hw;
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struct clk_init_data init;
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int ret;
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mux = kzalloc(sizeof(*mux), GFP_KERNEL);
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if (!mux)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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if (nodes->type_flag & CLK_MUX_READ_ONLY)
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init.ops = &zynqmp_clk_mux_ro_ops;
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else
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init.ops = &zynqmp_clk_mux_ops;
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init.flags = nodes->flag;
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init.parent_names = parents;
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init.num_parents = num_parents;
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mux->flags = nodes->type_flag;
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mux->hw.init = &init;
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mux->clk_id = clk_id;
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hw = &mux->hw;
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ret = clk_hw_register(NULL, hw);
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if (ret) {
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kfree(hw);
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hw = ERR_PTR(ret);
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}
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return hw;
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}
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EXPORT_SYMBOL_GPL(zynqmp_clk_register_mux);

‎drivers/clk/zynqmp/clk-zynqmp.h

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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2016-2018 Xilinx
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*/
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#ifndef __LINUX_CLK_ZYNQMP_H_
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#define __LINUX_CLK_ZYNQMP_H_
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#include <linux/spinlock.h>
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#include <linux/firmware/xlnx-zynqmp.h>
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/* Clock APIs payload parameters */
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#define CLK_GET_NAME_RESP_LEN 16
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#define CLK_GET_TOPOLOGY_RESP_WORDS 3
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#define CLK_GET_PARENTS_RESP_WORDS 3
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#define CLK_GET_ATTR_RESP_WORDS 1
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enum topology_type {
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TYPE_INVALID,
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TYPE_MUX,
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TYPE_PLL,
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TYPE_FIXEDFACTOR,
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TYPE_DIV1,
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TYPE_DIV2,
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TYPE_GATE,
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};
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/**
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* struct clock_topology - Clock topology
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* @type: Type of topology
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* @flag: Topology flags
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* @type_flag: Topology type specific flag
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*/
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struct clock_topology {
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u32 type;
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u32 flag;
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u32 type_flag;
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};
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struct clk_hw *zynqmp_clk_register_pll(const char *name, u32 clk_id,
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const char * const *parents,
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u8 num_parents,
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const struct clock_topology *nodes);
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struct clk_hw *zynqmp_clk_register_gate(const char *name, u32 clk_id,
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const char * const *parents,
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u8 num_parents,
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const struct clock_topology *nodes);
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struct clk_hw *zynqmp_clk_register_divider(const char *name,
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u32 clk_id,
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const char * const *parents,
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u8 num_parents,
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const struct clock_topology *nodes);
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struct clk_hw *zynqmp_clk_register_mux(const char *name, u32 clk_id,
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const char * const *parents,
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u8 num_parents,
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const struct clock_topology *nodes);
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struct clk_hw *zynqmp_clk_register_fixed_factor(const char *name,
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u32 clk_id,
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const char * const *parents,
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u8 num_parents,
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const struct clock_topology *nodes);
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#endif

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