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Peter Zijlstra (Intel)KAGA-KOKO
Peter Zijlstra (Intel)
authored and
KAGA-KOKO
committed
perf/x86/intel: Implement support for TSX Force Abort
Skylake (and later) will receive a microcode update to address a TSX errata. This microcode will, on execution of a TSX instruction (speculative or not) use (clobber) PMC3. This update will also provide a new MSR to change this behaviour along with a CPUID bit to enumerate the presence of this new MSR. When the MSR gets set; the microcode will no longer use PMC3 but will Force Abort every TSX transaction (upon executing COMMIT). When TSX Force Abort (TFA) is allowed (default); the MSR gets set when PMC3 gets scheduled and cleared when, after scheduling, PMC3 is unused. When TFA is not allowed; clear PMC3 from all constraints such that it will not get used. Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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2 files changed

+77
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lines changed

‎arch/x86/events/intel/core.c

Lines changed: 71 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1999,6 +1999,39 @@ static void intel_pmu_nhm_enable_all(int added)
19991999
intel_pmu_enable_all(added);
20002000
}
20012001

2002+
static void intel_set_tfa(struct cpu_hw_events *cpuc, bool on)
2003+
{
2004+
u64 val = on ? MSR_TFA_RTM_FORCE_ABORT : 0;
2005+
2006+
if (cpuc->tfa_shadow != val) {
2007+
cpuc->tfa_shadow = val;
2008+
wrmsrl(MSR_TSX_FORCE_ABORT, val);
2009+
}
2010+
}
2011+
2012+
static void intel_tfa_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr)
2013+
{
2014+
/*
2015+
* We're going to use PMC3, make sure TFA is set before we touch it.
2016+
*/
2017+
if (cntr == 3 && !cpuc->is_fake)
2018+
intel_set_tfa(cpuc, true);
2019+
}
2020+
2021+
static void intel_tfa_pmu_enable_all(int added)
2022+
{
2023+
struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2024+
2025+
/*
2026+
* If we find PMC3 is no longer used when we enable the PMU, we can
2027+
* clear TFA.
2028+
*/
2029+
if (!test_bit(3, cpuc->active_mask))
2030+
intel_set_tfa(cpuc, false);
2031+
2032+
intel_pmu_enable_all(added);
2033+
}
2034+
20022035
static void enable_counter_freeze(void)
20032036
{
20042037
update_debugctlmsr(get_debugctlmsr() |
@@ -3354,6 +3387,26 @@ glp_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
33543387
return c;
33553388
}
33563389

3390+
static bool allow_tsx_force_abort = true;
3391+
3392+
static struct event_constraint *
3393+
tfa_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3394+
struct perf_event *event)
3395+
{
3396+
struct event_constraint *c = hsw_get_event_constraints(cpuc, idx, event);
3397+
3398+
/*
3399+
* Without TFA we must not use PMC3.
3400+
*/
3401+
if (!allow_tsx_force_abort && test_bit(3, c->idxmsk)) {
3402+
c = dyn_constraint(cpuc, c, idx);
3403+
c->idxmsk64 &= ~(1ULL << 3);
3404+
c->weight--;
3405+
}
3406+
3407+
return c;
3408+
}
3409+
33573410
/*
33583411
* Broadwell:
33593412
*
@@ -3448,13 +3501,15 @@ int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu)
34483501
goto err;
34493502
}
34503503

3451-
if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
3504+
if (x86_pmu.flags & (PMU_FL_EXCL_CNTRS | PMU_FL_TFA)) {
34523505
size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint);
34533506

34543507
cpuc->constraint_list = kzalloc_node(sz, GFP_KERNEL, cpu_to_node(cpu));
34553508
if (!cpuc->constraint_list)
34563509
goto err_shared_regs;
3510+
}
34573511

3512+
if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
34583513
cpuc->excl_cntrs = allocate_excl_cntrs(cpu);
34593514
if (!cpuc->excl_cntrs)
34603515
goto err_constraint_list;
@@ -3564,9 +3619,10 @@ static void free_excl_cntrs(struct cpu_hw_events *cpuc)
35643619
if (c->core_id == -1 || --c->refcnt == 0)
35653620
kfree(c);
35663621
cpuc->excl_cntrs = NULL;
3567-
kfree(cpuc->constraint_list);
3568-
cpuc->constraint_list = NULL;
35693622
}
3623+
3624+
kfree(cpuc->constraint_list);
3625+
cpuc->constraint_list = NULL;
35703626
}
35713627

35723628
static void intel_pmu_cpu_dying(int cpu)
@@ -4086,8 +4142,11 @@ static struct attribute *intel_pmu_caps_attrs[] = {
40864142
NULL
40874143
};
40884144

4145+
DEVICE_BOOL_ATTR(allow_tsx_force_abort, 0644, allow_tsx_force_abort);
4146+
40894147
static struct attribute *intel_pmu_attrs[] = {
40904148
&dev_attr_freeze_on_smi.attr,
4149+
NULL, /* &dev_attr_allow_tsx_force_abort.attr.attr */
40914150
NULL,
40924151
};
40934152

@@ -4580,6 +4639,15 @@ __init int intel_pmu_init(void)
45804639
tsx_attr = hsw_tsx_events_attrs;
45814640
intel_pmu_pebs_data_source_skl(
45824641
boot_cpu_data.x86_model == INTEL_FAM6_SKYLAKE_X);
4642+
4643+
if (boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT)) {
4644+
x86_pmu.flags |= PMU_FL_TFA;
4645+
x86_pmu.get_event_constraints = tfa_get_event_constraints;
4646+
x86_pmu.enable_all = intel_tfa_pmu_enable_all;
4647+
x86_pmu.commit_scheduling = intel_tfa_commit_scheduling;
4648+
intel_pmu_attrs[1] = &dev_attr_allow_tsx_force_abort.attr.attr;
4649+
}
4650+
45834651
pr_cont("Skylake events, ");
45844652
name = "skylake";
45854653
break;

‎arch/x86/events/perf_event.h

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -242,6 +242,11 @@ struct cpu_hw_events {
242242
struct intel_excl_cntrs *excl_cntrs;
243243
int excl_thread_id; /* 0 or 1 */
244244

245+
/*
246+
* SKL TSX_FORCE_ABORT shadow
247+
*/
248+
u64 tfa_shadow;
249+
245250
/*
246251
* AMD specific bits
247252
*/
@@ -681,6 +686,7 @@ do { \
681686
#define PMU_FL_EXCL_CNTRS 0x4 /* has exclusive counter requirements */
682687
#define PMU_FL_EXCL_ENABLED 0x8 /* exclusive counter active */
683688
#define PMU_FL_PEBS_ALL 0x10 /* all events are valid PEBS events */
689+
#define PMU_FL_TFA 0x20 /* deal with TSX force abort */
684690

685691
#define EVENT_VAR(_id) event_attr_##_id
686692
#define EVENT_PTR(_id) &event_attr_##_id.attr.attr

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