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Merge branch 'drm-intel-fixes' of git://people.freedesktop.org/~danvet/drm-intel into drm-next
Daniel writes: "- Regression fixer for an OOPS at boot when i915.ko is built-in and CONFIG_PM=n, introduce in 3.5 (patch from Hunt Xu) - Regression fixer for occlusion query failures, the required w/a wasn't applied in all cases (thanks to Eric for tracking this on down). - dmar vs. dma_buf imprt fix (Dave Airlie) - 2 patches to fight down forcewake issues on snb. This is the stuff I've talked about 2 weeks ago already, it's a minefield. Investigation still going on, but afaict this is the best we have for now. - a few minor things to keep coverty&compiler happy (Alan, Davendra, Stéphane) - tons of hsw pci ids - this one is a bit late because internal approval sometimes takes a while, but ppl in charge finally agreed that world+dog already knows about ult and crw haswell variants ;-) Wrt regressions I'm aware of: - the power regression due to semaphores=1. Ben is running around with a killawatt, unfortunately we have a hard time reproducing this one. And this /shouldn't/ increase power usage. Ben has turned up a few odds bits though already. - the lvds fix in 3.6-rc1 broke a backlight after lid close/open (but can be resurrected with a modeset cycle). I guess we anger the bios - I'm still looking into this one. - gmbus broke edid reading on an odd-ball monitor, we need to fall-back. Due to vacation (both mine&the reporter's) this is stalling for a final patch and a tested-by on it. But issue is fully diagnosed." * 'drm-intel-fixes' of git://people.freedesktop.org/~danvet/drm-intel: drm/i915: correctly order the ring init sequence drm/i915: add more Haswell PCI IDs drm/i915: make rc6 in sysfs functions conditional drm/i915: Workaround hang with BSD and forcewake on SandyBridge drm/i915: Make intel_panel_get_backlight static. i915: don't map imported dma-bufs for dmar. drm/i915: remove unused variable drm/i915: Don't forget to apply SNB PIPE_CONTROL GTT workaround. drm/i915: fix forcewake related hangs on snb i915: Remove silly test i915: fix error path leak in intel_sdvo_write_cmd vlv: it might be wise if we initialised the flag value...
2 parents 0f457e4 + 0d8957c commit 41494cb

14 files changed

+172
-38
lines changed

‎drivers/char/agp/intel-agp.h

Lines changed: 34 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -239,16 +239,45 @@
239239
#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT2_IG 0x016A
240240
#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_HB 0x0F00 /* VLV1 */
241241
#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_IG 0x0F30
242-
#define PCI_DEVICE_ID_INTEL_HASWELL_HB 0x0400 /* Desktop */
242+
#define PCI_DEVICE_ID_INTEL_HASWELL_HB 0x0400 /* Desktop */
243243
#define PCI_DEVICE_ID_INTEL_HASWELL_D_GT1_IG 0x0402
244244
#define PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_IG 0x0412
245-
#define PCI_DEVICE_ID_INTEL_HASWELL_M_HB 0x0404 /* Mobile */
245+
#define PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_PLUS_IG 0x0422
246+
#define PCI_DEVICE_ID_INTEL_HASWELL_M_HB 0x0404 /* Mobile */
246247
#define PCI_DEVICE_ID_INTEL_HASWELL_M_GT1_IG 0x0406
247248
#define PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_IG 0x0416
248-
#define PCI_DEVICE_ID_INTEL_HASWELL_S_HB 0x0408 /* Server */
249+
#define PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_PLUS_IG 0x0426
250+
#define PCI_DEVICE_ID_INTEL_HASWELL_S_HB 0x0408 /* Server */
249251
#define PCI_DEVICE_ID_INTEL_HASWELL_S_GT1_IG 0x040a
250252
#define PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_IG 0x041a
251-
#define PCI_DEVICE_ID_INTEL_HASWELL_SDV 0x0c16 /* SDV */
252-
#define PCI_DEVICE_ID_INTEL_HASWELL_E_HB 0x0c04
253+
#define PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_PLUS_IG 0x042a
254+
#define PCI_DEVICE_ID_INTEL_HASWELL_E_HB 0x0c04
255+
#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT1_IG 0x0C02
256+
#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_IG 0x0C12
257+
#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_PLUS_IG 0x0C22
258+
#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT1_IG 0x0C06
259+
#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_IG 0x0C16
260+
#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_PLUS_IG 0x0C26
261+
#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT1_IG 0x0C0A
262+
#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_IG 0x0C1A
263+
#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_PLUS_IG 0x0C2A
264+
#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT1_IG 0x0A02
265+
#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_IG 0x0A12
266+
#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_PLUS_IG 0x0A22
267+
#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT1_IG 0x0A06
268+
#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_IG 0x0A16
269+
#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_PLUS_IG 0x0A26
270+
#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT1_IG 0x0A0A
271+
#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_IG 0x0A1A
272+
#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_PLUS_IG 0x0A2A
273+
#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT1_IG 0x0D12
274+
#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_IG 0x0D22
275+
#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_PLUS_IG 0x0D32
276+
#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT1_IG 0x0D16
277+
#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_IG 0x0D26
278+
#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_PLUS_IG 0x0D36
279+
#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT1_IG 0x0D1A
280+
#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_IG 0x0D2A
281+
#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_PLUS_IG 0x0D3A
253282

254283
#endif

‎drivers/char/agp/intel-gtt.c

Lines changed: 59 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1502,15 +1502,73 @@ static const struct intel_gtt_driver_description {
15021502
"Haswell", &sandybridge_gtt_driver },
15031503
{ PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_IG,
15041504
"Haswell", &sandybridge_gtt_driver },
1505+
{ PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_PLUS_IG,
1506+
"Haswell", &sandybridge_gtt_driver },
15051507
{ PCI_DEVICE_ID_INTEL_HASWELL_M_GT1_IG,
15061508
"Haswell", &sandybridge_gtt_driver },
15071509
{ PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_IG,
15081510
"Haswell", &sandybridge_gtt_driver },
1511+
{ PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_PLUS_IG,
1512+
"Haswell", &sandybridge_gtt_driver },
15091513
{ PCI_DEVICE_ID_INTEL_HASWELL_S_GT1_IG,
15101514
"Haswell", &sandybridge_gtt_driver },
15111515
{ PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_IG,
15121516
"Haswell", &sandybridge_gtt_driver },
1513-
{ PCI_DEVICE_ID_INTEL_HASWELL_SDV,
1517+
{ PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_PLUS_IG,
1518+
"Haswell", &sandybridge_gtt_driver },
1519+
{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT1_IG,
1520+
"Haswell", &sandybridge_gtt_driver },
1521+
{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_IG,
1522+
"Haswell", &sandybridge_gtt_driver },
1523+
{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_PLUS_IG,
1524+
"Haswell", &sandybridge_gtt_driver },
1525+
{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT1_IG,
1526+
"Haswell", &sandybridge_gtt_driver },
1527+
{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_IG,
1528+
"Haswell", &sandybridge_gtt_driver },
1529+
{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_PLUS_IG,
1530+
"Haswell", &sandybridge_gtt_driver },
1531+
{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT1_IG,
1532+
"Haswell", &sandybridge_gtt_driver },
1533+
{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_IG,
1534+
"Haswell", &sandybridge_gtt_driver },
1535+
{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_PLUS_IG,
1536+
"Haswell", &sandybridge_gtt_driver },
1537+
{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT1_IG,
1538+
"Haswell", &sandybridge_gtt_driver },
1539+
{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_IG,
1540+
"Haswell", &sandybridge_gtt_driver },
1541+
{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_PLUS_IG,
1542+
"Haswell", &sandybridge_gtt_driver },
1543+
{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT1_IG,
1544+
"Haswell", &sandybridge_gtt_driver },
1545+
{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_IG,
1546+
"Haswell", &sandybridge_gtt_driver },
1547+
{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_PLUS_IG,
1548+
"Haswell", &sandybridge_gtt_driver },
1549+
{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT1_IG,
1550+
"Haswell", &sandybridge_gtt_driver },
1551+
{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_IG,
1552+
"Haswell", &sandybridge_gtt_driver },
1553+
{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_PLUS_IG,
1554+
"Haswell", &sandybridge_gtt_driver },
1555+
{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT1_IG,
1556+
"Haswell", &sandybridge_gtt_driver },
1557+
{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_IG,
1558+
"Haswell", &sandybridge_gtt_driver },
1559+
{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_PLUS_IG,
1560+
"Haswell", &sandybridge_gtt_driver },
1561+
{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT1_IG,
1562+
"Haswell", &sandybridge_gtt_driver },
1563+
{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_IG,
1564+
"Haswell", &sandybridge_gtt_driver },
1565+
{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_PLUS_IG,
1566+
"Haswell", &sandybridge_gtt_driver },
1567+
{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT1_IG,
1568+
"Haswell", &sandybridge_gtt_driver },
1569+
{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_IG,
1570+
"Haswell", &sandybridge_gtt_driver },
1571+
{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_PLUS_IG,
15141572
"Haswell", &sandybridge_gtt_driver },
15151573
{ 0, NULL, NULL }
15161574
};

‎drivers/gpu/drm/i915/i915_drv.c

Lines changed: 30 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -346,11 +346,40 @@ static const struct pci_device_id pciidlist[] = { /* aka */
346346
INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
347347
INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
348348
INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
349+
INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT2 desktop */
349350
INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
350351
INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
352+
INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT2 server */
351353
INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
352354
INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
353-
INTEL_VGA_DEVICE(0x0c16, &intel_haswell_d_info), /* SDV */
355+
INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */
356+
INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */
357+
INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */
358+
INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT2 desktop */
359+
INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */
360+
INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */
361+
INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT2 server */
362+
INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */
363+
INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */
364+
INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT2 mobile */
365+
INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */
366+
INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */
367+
INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT2 desktop */
368+
INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */
369+
INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */
370+
INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT2 server */
371+
INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */
372+
INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */
373+
INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT2 mobile */
374+
INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT1 desktop */
375+
INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT2 desktop */
376+
INTEL_VGA_DEVICE(0x0D32, &intel_haswell_d_info), /* CRW GT2 desktop */
377+
INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT1 server */
378+
INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT2 server */
379+
INTEL_VGA_DEVICE(0x0D3A, &intel_haswell_d_info), /* CRW GT2 server */
380+
INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT1 mobile */
381+
INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */
382+
INTEL_VGA_DEVICE(0x0D36, &intel_haswell_m_info), /* CRW GT2 mobile */
354383
INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
355384
INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
356385
INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),

‎drivers/gpu/drm/i915/i915_gem_context.c

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -451,7 +451,6 @@ int i915_switch_context(struct intel_ring_buffer *ring,
451451
struct drm_i915_file_private *file_priv = NULL;
452452
struct i915_hw_context *to;
453453
struct drm_i915_gem_object *from_obj = ring->last_context_obj;
454-
int ret;
455454

456455
if (dev_priv->hw_contexts_disabled)
457456
return 0;

‎drivers/gpu/drm/i915/i915_gem_execbuffer.c

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -291,6 +291,16 @@ i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
291291
target_i915_obj = to_intel_bo(target_obj);
292292
target_offset = target_i915_obj->gtt_offset;
293293

294+
/* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
295+
* pipe_control writes because the gpu doesn't properly redirect them
296+
* through the ppgtt for non_secure batchbuffers. */
297+
if (unlikely(IS_GEN6(dev) &&
298+
reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION &&
299+
!target_i915_obj->has_global_gtt_mapping)) {
300+
i915_gem_gtt_bind_object(target_i915_obj,
301+
target_i915_obj->cache_level);
302+
}
303+
294304
/* The target buffer should have appeared before us in the
295305
* exec_object list, so it should have a GTT space bound by now.
296306
*/
@@ -399,16 +409,6 @@ i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
399409
io_mapping_unmap_atomic(reloc_page);
400410
}
401411

402-
/* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
403-
* pipe_control writes because the gpu doesn't properly redirect them
404-
* through the ppgtt for non_secure batchbuffers. */
405-
if (unlikely(IS_GEN6(dev) &&
406-
reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION &&
407-
!target_i915_obj->has_global_gtt_mapping)) {
408-
i915_gem_gtt_bind_object(target_i915_obj,
409-
target_i915_obj->cache_level);
410-
}
411-
412412
/* and update the user's relocation entry */
413413
reloc->presumed_offset = target_offset;
414414

‎drivers/gpu/drm/i915/i915_gem_gtt.c

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -361,7 +361,8 @@ int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
361361
struct drm_device *dev = obj->base.dev;
362362
struct drm_i915_private *dev_priv = dev->dev_private;
363363

364-
if (dev_priv->mm.gtt->needs_dmar)
364+
/* don't map imported dma buf objects */
365+
if (dev_priv->mm.gtt->needs_dmar && !obj->sg_table)
365366
return intel_gtt_map_memory(obj->pages,
366367
obj->base.size >> PAGE_SHIFT,
367368
&obj->sg_list,

‎drivers/gpu/drm/i915/i915_sysfs.c

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -32,6 +32,7 @@
3232
#include "intel_drv.h"
3333
#include "i915_drv.h"
3434

35+
#ifdef CONFIG_PM
3536
static u32 calc_residency(struct drm_device *dev, const u32 reg)
3637
{
3738
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -224,3 +225,14 @@ void i915_teardown_sysfs(struct drm_device *dev)
224225
device_remove_bin_file(&dev->primary->kdev, &dpf_attrs);
225226
sysfs_unmerge_group(&dev->primary->kdev.kobj, &rc6_attr_group);
226227
}
228+
#else
229+
void i915_setup_sysfs(struct drm_device *dev)
230+
{
231+
return;
232+
}
233+
234+
void i915_teardown_sysfs(struct drm_device *dev)
235+
{
236+
return;
237+
}
238+
#endif /* CONFIG_PM */

‎drivers/gpu/drm/i915/intel_display.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -869,6 +869,7 @@ intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
869869
unsigned long bestppm, ppm, absppm;
870870
int dotclk, flag;
871871

872+
flag = 0;
872873
dotclk = target * 1000;
873874
bestppm = 1000000;
874875
ppm = absppm = 0;

‎drivers/gpu/drm/i915/intel_drv.h

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -46,15 +46,16 @@
4646
})
4747

4848
#define wait_for_atomic_us(COND, US) ({ \
49-
int i, ret__ = -ETIMEDOUT; \
50-
for (i = 0; i < (US); i++) { \
51-
if ((COND)) { \
52-
ret__ = 0; \
53-
break; \
54-
} \
55-
udelay(1); \
56-
} \
57-
ret__; \
49+
unsigned long timeout__ = jiffies + usecs_to_jiffies(US); \
50+
int ret__ = 0; \
51+
while (!(COND)) { \
52+
if (time_after(jiffies, timeout__)) { \
53+
ret__ = -ETIMEDOUT; \
54+
break; \
55+
} \
56+
cpu_relax(); \
57+
} \
58+
ret__; \
5859
})
5960

6061
#define wait_for(COND, MS) _wait_for(COND, MS, 1)
@@ -380,7 +381,6 @@ extern void intel_pch_panel_fitting(struct drm_device *dev,
380381
const struct drm_display_mode *mode,
381382
struct drm_display_mode *adjusted_mode);
382383
extern u32 intel_panel_get_max_backlight(struct drm_device *dev);
383-
extern u32 intel_panel_get_backlight(struct drm_device *dev);
384384
extern void intel_panel_set_backlight(struct drm_device *dev, u32 level);
385385
extern int intel_panel_setup_backlight(struct drm_device *dev);
386386
extern void intel_panel_enable_backlight(struct drm_device *dev,

‎drivers/gpu/drm/i915/intel_i2c.c

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -540,9 +540,6 @@ void intel_teardown_gmbus(struct drm_device *dev)
540540
struct drm_i915_private *dev_priv = dev->dev_private;
541541
int i;
542542

543-
if (dev_priv->gmbus == NULL)
544-
return;
545-
546543
for (i = 0; i < GMBUS_NUM_PORTS; i++) {
547544
struct intel_gmbus *bus = &dev_priv->gmbus[i];
548545
i2c_del_adapter(&bus->adapter);

‎drivers/gpu/drm/i915/intel_panel.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -213,7 +213,7 @@ static u32 intel_panel_compute_brightness(struct drm_device *dev, u32 val)
213213
return val;
214214
}
215215

216-
u32 intel_panel_get_backlight(struct drm_device *dev)
216+
static u32 intel_panel_get_backlight(struct drm_device *dev)
217217
{
218218
struct drm_i915_private *dev_priv = dev->dev_private;
219219
u32 val;

‎drivers/gpu/drm/i915/intel_pm.c

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3963,6 +3963,7 @@ static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
39633963
DRM_ERROR("Force wake wait timed out\n");
39643964

39653965
I915_WRITE_NOTRACE(FORCEWAKE, 1);
3966+
POSTING_READ(FORCEWAKE);
39663967

39673968
if (wait_for_atomic_us((I915_READ_NOTRACE(forcewake_ack) & 1), 500))
39683969
DRM_ERROR("Force wake wait timed out\n");
@@ -3983,6 +3984,7 @@ static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
39833984
DRM_ERROR("Force wake wait timed out\n");
39843985

39853986
I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(1));
3987+
POSTING_READ(FORCEWAKE_MT);
39863988

39873989
if (wait_for_atomic_us((I915_READ_NOTRACE(forcewake_ack) & 1), 500))
39883990
DRM_ERROR("Force wake wait timed out\n");
@@ -4018,14 +4020,14 @@ void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
40184020
static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
40194021
{
40204022
I915_WRITE_NOTRACE(FORCEWAKE, 0);
4021-
/* The below doubles as a POSTING_READ */
4023+
POSTING_READ(FORCEWAKE);
40224024
gen6_gt_check_fifodbg(dev_priv);
40234025
}
40244026

40254027
static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
40264028
{
40274029
I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(1));
4028-
/* The below doubles as a POSTING_READ */
4030+
POSTING_READ(FORCEWAKE_MT);
40294031
gen6_gt_check_fifodbg(dev_priv);
40304032
}
40314033

‎drivers/gpu/drm/i915/intel_ringbuffer.c

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -289,8 +289,6 @@ static int init_ring_common(struct intel_ring_buffer *ring)
289289
I915_WRITE_HEAD(ring, 0);
290290
ring->write_tail(ring, 0);
291291

292-
/* Initialize the ring. */
293-
I915_WRITE_START(ring, obj->gtt_offset);
294292
head = I915_READ_HEAD(ring) & HEAD_ADDR;
295293

296294
/* G45 ring initialization fails to reset head to zero */
@@ -316,6 +314,11 @@ static int init_ring_common(struct intel_ring_buffer *ring)
316314
}
317315
}
318316

317+
/* Initialize the ring. This must happen _after_ we've cleared the ring
318+
* registers with the above sequence (the readback of the HEAD registers
319+
* also enforces ordering), otherwise the hw might lose the new ring
320+
* register values. */
321+
I915_WRITE_START(ring, obj->gtt_offset);
319322
I915_WRITE_CTL(ring,
320323
((ring->size - PAGE_SIZE) & RING_NR_PAGES)
321324
| RING_VALID);

‎drivers/gpu/drm/i915/intel_sdvo.c

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -444,13 +444,16 @@ static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
444444
struct i2c_msg *msgs;
445445
int i, ret = true;
446446

447+
/* Would be simpler to allocate both in one go ? */
447448
buf = (u8 *)kzalloc(args_len * 2 + 2, GFP_KERNEL);
448449
if (!buf)
449450
return false;
450451

451452
msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL);
452-
if (!msgs)
453+
if (!msgs) {
454+
kfree(buf);
453455
return false;
456+
}
454457

455458
intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
456459

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