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Merge tag 'arc-4.10-rc1-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc
Pull more ARC updates from Vineet Gupta: - Fix for aliasing VIPT dcache in old ARC700 cores - micro-optimization in ARC700 ProtV handler - Enable SG_CHAIN [Vladimir] - ARC HS38 core intc default to prio 1 * tag 'arc-4.10-rc1-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc: ARC: mm: arc700: Don't assume 2 colours for aliasing VIPT dcache ARC: mm: No need to save cache version in @cpuinfo ARC: enable SG chaining ARCv2: intc: default all interrupts to priority 1 ARCv2: entry: document intr disable in hard isr ARC: ARCompact entry: elide re-reading ECR in ProtV handler
2 parents 50f6584 + 08fe007 commit 42e0372

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-35
lines changed

9 files changed

+46
-35
lines changed

‎Documentation/features/io/sg-chain/arch-support.txt

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@
77
| arch |status|
88
-----------------------
99
| alpha: | TODO |
10-
| arc: | TODO |
10+
| arc: | ok |
1111
| arm: | ok |
1212
| arm64: | ok |
1313
| avr32: | TODO |

‎arch/arc/Kconfig

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,7 @@
99
config ARC
1010
def_bool y
1111
select ARC_TIMERS
12+
select ARCH_HAS_SG_CHAIN
1213
select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC
1314
select BUILDTIME_EXTABLE_SORT
1415
select CLONE_BACKWARDS

‎arch/arc/include/asm/arcregs.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -244,7 +244,7 @@ struct cpuinfo_arc_mmu {
244244
};
245245

246246
struct cpuinfo_arc_cache {
247-
unsigned int sz_k:14, line_len:8, assoc:4, ver:4, alias:1, vipt:1;
247+
unsigned int sz_k:14, line_len:8, assoc:4, alias:1, vipt:1, pad:4;
248248
};
249249

250250
struct cpuinfo_arc_bpu {

‎arch/arc/include/asm/cacheflush.h

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -85,6 +85,10 @@ void flush_anon_page(struct vm_area_struct *vma,
8585
*/
8686
#define PG_dc_clean PG_arch_1
8787

88+
#define CACHE_COLORS_NUM 4
89+
#define CACHE_COLORS_MSK (CACHE_COLORS_NUM - 1)
90+
#define CACHE_COLOR(addr) (((unsigned long)(addr) >> (PAGE_SHIFT)) & CACHE_COLORS_MSK)
91+
8892
/*
8993
* Simple wrapper over config option
9094
* Bootup code ensures that hardware matches kernel configuration
@@ -94,8 +98,6 @@ static inline int cache_is_vipt_aliasing(void)
9498
return IS_ENABLED(CONFIG_ARC_CACHE_VIPT_ALIASING);
9599
}
96100

97-
#define CACHE_COLOR(addr) (((unsigned long)(addr) >> (PAGE_SHIFT)) & 1)
98-
99101
/*
100102
* checks if two addresses (after page aligning) index into same cache set
101103
*/

‎arch/arc/include/asm/irqflags-arcv2.h

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -38,10 +38,10 @@
3838
#define AUX_IRQ_ACT_BIT_U 31
3939

4040
/*
41-
* User space should be interruptable even by lowest prio interrupt
42-
* Safe even if actual interrupt priorities is fewer or even one
41+
* Hardware supports 16 priorities (0 highest, 15 lowest)
42+
* Linux by default runs at 1, priority 0 reserved for NMI style interrupts
4343
*/
44-
#define ARCV2_IRQ_DEF_PRIO 15
44+
#define ARCV2_IRQ_DEF_PRIO 1
4545

4646
/* seed value for status register */
4747
#define ISA_INIT_STATUS_BITS (STATUS_IE_MASK | STATUS_AD_MASK | \

‎arch/arc/kernel/entry-arcv2.S

Lines changed: 18 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -67,12 +67,23 @@ ENTRY(handle_interrupt)
6767

6868
INTERRUPT_PROLOGUE irq
6969

70-
clri ; To make status32.IE agree with CPU internal state
71-
72-
#ifdef CONFIG_TRACE_IRQFLAGS
73-
TRACE_ASM_IRQ_DISABLE
74-
#endif
75-
70+
# irq control APIs local_irq_save/restore/disable/enable fiddle with
71+
# global interrupt enable bits in STATUS32 (.IE for 1 prio, .E[] for 2 prio)
72+
# However a taken interrupt doesn't clear these bits. Thus irqs_disabled()
73+
# query in hard ISR path would return false (since .IE is set) which would
74+
# trips genirq interrupt handling asserts.
75+
#
76+
# So do a "soft" disable of interrutps here.
77+
#
78+
# Note this disable is only for consistent book-keeping as further interrupts
79+
# will be disabled anyways even w/o this. Hardware tracks active interrupts
80+
# seperately in AUX_IRQ_ACTIVE.active and will not take new interrupts
81+
# unless this one returns (or higher prio becomes pending in 2-prio scheme)
82+
83+
IRQ_DISABLE
84+
85+
; icause is banked: one per priority level
86+
; so a higher prio interrupt taken here won't clobber prev prio icause
7687
lr r0, [ICAUSE]
7788
mov blink, ret_from_exception
7889

@@ -171,6 +182,7 @@ END(EV_TLBProtV)
171182
; All 2 entry points to here already disable interrupts
172183

173184
.Lrestore_regs:
185+
restore_regs:
174186

175187
# Interrpts are actually disabled from this point on, but will get
176188
# reenabled after we return from interrupt/exception.

‎arch/arc/kernel/entry-compact.S

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -259,7 +259,7 @@ ENTRY(EV_TLBProtV)
259259

260260
EXCEPTION_PROLOGUE
261261

262-
lr r2, [ecr]
262+
mov r2, r9 ; ECR set into r9 already
263263
lr r0, [efa] ; Faulting Data address (not part of pt_regs saved above)
264264

265265
; Exception auto-disables further Intr/exceptions.

‎arch/arc/kernel/intc-arcv2.c

Lines changed: 4 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -14,8 +14,6 @@
1414
#include <linux/irqchip.h>
1515
#include <asm/irq.h>
1616

17-
static int irq_prio;
18-
1917
/*
2018
* Early Hardware specific Interrupt setup
2119
* -Called very early (start_kernel -> setup_arch -> setup_processor)
@@ -24,7 +22,7 @@ static int irq_prio;
2422
*/
2523
void arc_init_IRQ(void)
2624
{
27-
unsigned int tmp;
25+
unsigned int tmp, irq_prio;
2826

2927
struct irq_build {
3028
#ifdef CONFIG_CPU_BIG_ENDIAN
@@ -67,12 +65,12 @@ void arc_init_IRQ(void)
6765

6866
irq_prio = irq_bcr.prio; /* Encoded as N-1 for N levels */
6967
pr_info("archs-intc\t: %d priority levels (default %d)%s\n",
70-
irq_prio + 1, irq_prio,
68+
irq_prio + 1, ARCV2_IRQ_DEF_PRIO,
7169
irq_bcr.firq ? " FIRQ (not used)":"");
7270

7371
/* setup status32, don't enable intr yet as kernel doesn't want */
7472
tmp = read_aux_reg(0xa);
75-
tmp |= STATUS_AD_MASK | (irq_prio << 1);
73+
tmp |= STATUS_AD_MASK | (ARCV2_IRQ_DEF_PRIO << 1);
7674
tmp &= ~STATUS_IE_MASK;
7775
asm volatile("kflag %0 \n"::"r"(tmp));
7876
}
@@ -93,7 +91,7 @@ void arcv2_irq_enable(struct irq_data *data)
9391
{
9492
/* set default priority */
9593
write_aux_reg(AUX_IRQ_SELECT, data->irq);
96-
write_aux_reg(AUX_IRQ_PRIORITY, irq_prio);
94+
write_aux_reg(AUX_IRQ_PRIORITY, ARCV2_IRQ_DEF_PRIO);
9795

9896
/*
9997
* hw auto enables (linux unmask) all by default

‎arch/arc/mm/cache.c

Lines changed: 13 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -40,7 +40,7 @@ char *arc_cache_mumbojumbo(int c, char *buf, int len)
4040
struct cpuinfo_arc_cache *p;
4141

4242
#define PR_CACHE(p, cfg, str) \
43-
if (!(p)->ver) \
43+
if (!(p)->line_len) \
4444
n += scnprintf(buf + n, len - n, str"\t\t: N/A\n"); \
4545
else \
4646
n += scnprintf(buf + n, len - n, \
@@ -54,7 +54,7 @@ char *arc_cache_mumbojumbo(int c, char *buf, int len)
5454
PR_CACHE(&cpuinfo_arc700[c].dcache, CONFIG_ARC_HAS_DCACHE, "D-Cache");
5555

5656
p = &cpuinfo_arc700[c].slc;
57-
if (p->ver)
57+
if (p->line_len)
5858
n += scnprintf(buf + n, len - n,
5959
"SLC\t\t: %uK, %uB Line%s\n",
6060
p->sz_k, p->line_len, IS_USED_RUN(slc_enable));
@@ -104,7 +104,6 @@ static void read_decode_cache_bcr_arcv2(int cpu)
104104
READ_BCR(ARC_REG_SLC_BCR, sbcr);
105105
if (sbcr.ver) {
106106
READ_BCR(ARC_REG_SLC_CFG, slc_cfg);
107-
p_slc->ver = sbcr.ver;
108107
p_slc->sz_k = 128 << slc_cfg.sz;
109108
l2_line_sz = p_slc->line_len = (slc_cfg.lsz == 0) ? 128 : 64;
110109
}
@@ -152,7 +151,6 @@ void read_decode_cache_bcr(void)
152151

153152
p_ic->line_len = 8 << ibcr.line_len;
154153
p_ic->sz_k = 1 << (ibcr.sz - 1);
155-
p_ic->ver = ibcr.ver;
156154
p_ic->vipt = 1;
157155
p_ic->alias = p_ic->sz_k/p_ic->assoc/TO_KB(PAGE_SIZE) > 1;
158156

@@ -176,7 +174,6 @@ void read_decode_cache_bcr(void)
176174

177175
p_dc->line_len = 16 << dbcr.line_len;
178176
p_dc->sz_k = 1 << (dbcr.sz - 1);
179-
p_dc->ver = dbcr.ver;
180177

181178
slc_chk:
182179
if (is_isa_arcv2())
@@ -945,17 +942,13 @@ void arc_cache_init(void)
945942
if (IS_ENABLED(CONFIG_ARC_HAS_ICACHE)) {
946943
struct cpuinfo_arc_cache *ic = &cpuinfo_arc700[cpu].icache;
947944

948-
if (!ic->ver)
945+
if (!ic->line_len)
949946
panic("cache support enabled but non-existent cache\n");
950947

951948
if (ic->line_len != L1_CACHE_BYTES)
952949
panic("ICache line [%d] != kernel Config [%d]",
953950
ic->line_len, L1_CACHE_BYTES);
954951

955-
if (ic->ver != CONFIG_ARC_MMU_VER)
956-
panic("Cache ver [%d] doesn't match MMU ver [%d]\n",
957-
ic->ver, CONFIG_ARC_MMU_VER);
958-
959952
/*
960953
* In MMU v4 (HS38x) the aliasing icache config uses IVIL/PTAG
961954
* pair to provide vaddr/paddr respectively, just as in MMU v3
@@ -969,7 +962,7 @@ void arc_cache_init(void)
969962
if (IS_ENABLED(CONFIG_ARC_HAS_DCACHE)) {
970963
struct cpuinfo_arc_cache *dc = &cpuinfo_arc700[cpu].dcache;
971964

972-
if (!dc->ver)
965+
if (!dc->line_len)
973966
panic("cache support enabled but non-existent cache\n");
974967

975968
if (dc->line_len != L1_CACHE_BYTES)
@@ -979,11 +972,16 @@ void arc_cache_init(void)
979972
/* check for D-Cache aliasing on ARCompact: ARCv2 has PIPT */
980973
if (is_isa_arcompact()) {
981974
int handled = IS_ENABLED(CONFIG_ARC_CACHE_VIPT_ALIASING);
982-
983-
if (dc->alias && !handled)
984-
panic("Enable CONFIG_ARC_CACHE_VIPT_ALIASING\n");
985-
else if (!dc->alias && handled)
975+
int num_colors = dc->sz_k/dc->assoc/TO_KB(PAGE_SIZE);
976+
977+
if (dc->alias) {
978+
if (!handled)
979+
panic("Enable CONFIG_ARC_CACHE_VIPT_ALIASING\n");
980+
if (CACHE_COLORS_NUM != num_colors)
981+
panic("CACHE_COLORS_NUM not optimized for config\n");
982+
} else if (!dc->alias && handled) {
986983
panic("Disable CONFIG_ARC_CACHE_VIPT_ALIASING\n");
984+
}
987985
}
988986
}
989987

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