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torvaldstorvalds
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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/lliubbo/blackfin
Pull blackfin update from Bob Liu. * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/lliubbo/blackfin: blackfin: SEC: clean up SEC interrupt initialization blackfin: kgdb: call generic_exec_single() directly blackfin: anomaly: add anomaly 16000030 for bf5xx Blackfin: dpmc: use module_platform_driver macro Blackfin: remove unused is_in_rom() Blackfin: remove unnecessary prototype for kobjsize() Blackfin: twi: Add missing __iomem annotation Blackfin: Annotate strnlen_user and strlen_user 'src' parameter with __user Blackfin: Annotate clear_user 'to' parameter with __user Blackfin: Add missing __user annotations to put_user Blackfin: Annotate strncpy_from_user src parameter with __user blackfin: Use Kbuild infrastructure for kvm_para.h UAPI: (Scripted) Disintegrate arch/blackfin/include/asm
2 parents 3d9de19 + 86794b4 commit 4351654

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38 files changed

+972
-948
lines changed

38 files changed

+972
-948
lines changed

‎arch/blackfin/include/asm/Kbuild

Lines changed: 1 addition & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,3 @@
1-
include include/asm-generic/Kbuild.asm
21

32
generic-y += auxvec.h
43
generic-y += bitsperlong.h
@@ -17,6 +16,7 @@ generic-y += ipcbuf.h
1716
generic-y += irq_regs.h
1817
generic-y += kdebug.h
1918
generic-y += kmap_types.h
19+
generic-y += kvm_para.h
2020
generic-y += local64.h
2121
generic-y += local.h
2222
generic-y += mman.h
@@ -44,7 +44,3 @@ generic-y += ucontext.h
4444
generic-y += unaligned.h
4545
generic-y += user.h
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generic-y += xor.h
47-
48-
header-y += bfin_sport.h
49-
header-y += cachectl.h
50-
header-y += fixed_code.h

‎arch/blackfin/include/asm/bfin_sport.h

Lines changed: 1 addition & 127 deletions
Original file line numberDiff line numberDiff line change
@@ -5,65 +5,12 @@
55
*
66
* Licensed under the GPL-2 or later.
77
*/
8-
98
#ifndef __BFIN_SPORT_H__
109
#define __BFIN_SPORT_H__
1110

12-
/* Sport mode: it can be set to TDM, i2s or others */
13-
#define NORM_MODE 0x0
14-
#define TDM_MODE 0x1
15-
#define I2S_MODE 0x2
16-
#define NDSO_MODE 0x3
17-
18-
/* Data format, normal, a-law or u-law */
19-
#define NORM_FORMAT 0x0
20-
#define ALAW_FORMAT 0x2
21-
#define ULAW_FORMAT 0x3
22-
23-
/* Function driver which use sport must initialize the structure */
24-
struct sport_config {
25-
/* TDM (multichannels), I2S or other mode */
26-
unsigned int mode:3;
27-
unsigned int polled; /* use poll instead of irq when set */
28-
29-
/* if TDM mode is selected, channels must be set */
30-
int channels; /* Must be in 8 units */
31-
unsigned int frame_delay:4; /* Delay between frame sync pulse and first bit */
32-
33-
/* I2S mode */
34-
unsigned int right_first:1; /* Right stereo channel first */
35-
36-
/* In mormal mode, the following item need to be set */
37-
unsigned int lsb_first:1; /* order of transmit or receive data */
38-
unsigned int fsync:1; /* Frame sync required */
39-
unsigned int data_indep:1; /* data independent frame sync generated */
40-
unsigned int act_low:1; /* Active low TFS */
41-
unsigned int late_fsync:1; /* Late frame sync */
42-
unsigned int tckfe:1;
43-
unsigned int sec_en:1; /* Secondary side enabled */
44-
45-
/* Choose clock source */
46-
unsigned int int_clk:1; /* Internal or external clock */
47-
48-
/* If external clock is used, the following fields are ignored */
49-
int serial_clk;
50-
int fsync_clk;
51-
52-
unsigned int data_format:2; /* Normal, u-law or a-law */
53-
54-
int word_len; /* How length of the word in bits, 3-32 bits */
55-
int dma_enabled;
56-
};
57-
58-
/* Userspace interface */
59-
#define SPORT_IOC_MAGIC 'P'
60-
#define SPORT_IOC_CONFIG _IOWR('P', 0x01, struct sport_config)
61-
#define SPORT_IOC_GET_SYSTEMCLOCK _IOR('P', 0x02, unsigned long)
62-
#define SPORT_IOC_SET_BAUDRATE _IOW('P', 0x03, unsigned long)
63-
64-
#ifdef __KERNEL__
6511

6612
#include <linux/types.h>
13+
#include <uapi/asm/bfin_sport.h>
6714

6815
/*
6916
* All Blackfin system MMRs are padded to 32bits even if the register
@@ -122,76 +69,3 @@ struct bfin_snd_platform_data {
12269
})
12370

12471
#endif
125-
126-
/* SPORT_TCR1 Masks */
127-
#define TSPEN 0x0001 /* TX enable */
128-
#define ITCLK 0x0002 /* Internal TX Clock Select */
129-
#define TDTYPE 0x000C /* TX Data Formatting Select */
130-
#define DTYPE_NORM 0x0000 /* Data Format Normal */
131-
#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
132-
#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
133-
#define TLSBIT 0x0010 /* TX Bit Order */
134-
#define ITFS 0x0200 /* Internal TX Frame Sync Select */
135-
#define TFSR 0x0400 /* TX Frame Sync Required Select */
136-
#define DITFS 0x0800 /* Data Independent TX Frame Sync Select */
137-
#define LTFS 0x1000 /* Low TX Frame Sync Select */
138-
#define LATFS 0x2000 /* Late TX Frame Sync Select */
139-
#define TCKFE 0x4000 /* TX Clock Falling Edge Select */
140-
141-
/* SPORT_TCR2 Masks */
142-
#define SLEN 0x001F /* SPORT TX Word Length (2 - 31) */
143-
#define DP_SLEN(x) BFIN_DEPOSIT(SLEN, x)
144-
#define EX_SLEN(x) BFIN_EXTRACT(SLEN, x)
145-
#define TXSE 0x0100 /* TX Secondary Enable */
146-
#define TSFSE 0x0200 /* TX Stereo Frame Sync Enable */
147-
#define TRFST 0x0400 /* TX Right-First Data Order */
148-
149-
/* SPORT_RCR1 Masks */
150-
#define RSPEN 0x0001 /* RX enable */
151-
#define IRCLK 0x0002 /* Internal RX Clock Select */
152-
#define RDTYPE 0x000C /* RX Data Formatting Select */
153-
/* DTYPE_* defined above */
154-
#define RLSBIT 0x0010 /* RX Bit Order */
155-
#define IRFS 0x0200 /* Internal RX Frame Sync Select */
156-
#define RFSR 0x0400 /* RX Frame Sync Required Select */
157-
#define LRFS 0x1000 /* Low RX Frame Sync Select */
158-
#define LARFS 0x2000 /* Late RX Frame Sync Select */
159-
#define RCKFE 0x4000 /* RX Clock Falling Edge Select */
160-
161-
/* SPORT_RCR2 Masks */
162-
/* SLEN defined above */
163-
#define RXSE 0x0100 /* RX Secondary Enable */
164-
#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */
165-
#define RRFST 0x0400 /* Right-First Data Order */
166-
167-
/* SPORT_STAT Masks */
168-
#define RXNE 0x0001 /* RX FIFO Not Empty Status */
169-
#define RUVF 0x0002 /* RX Underflow Status */
170-
#define ROVF 0x0004 /* RX Overflow Status */
171-
#define TXF 0x0008 /* TX FIFO Full Status */
172-
#define TUVF 0x0010 /* TX Underflow Status */
173-
#define TOVF 0x0020 /* TX Overflow Status */
174-
#define TXHRE 0x0040 /* TX Hold Register Empty */
175-
176-
/* SPORT_MCMC1 Masks */
177-
#define SP_WOFF 0x03FF /* Multichannel Window Offset Field */
178-
#define DP_SP_WOFF(x) BFIN_DEPOSIT(SP_WOFF, x)
179-
#define EX_SP_WOFF(x) BFIN_EXTRACT(SP_WOFF, x)
180-
#define SP_WSIZE 0xF000 /* Multichannel Window Size Field */
181-
#define DP_SP_WSIZE(x) BFIN_DEPOSIT(SP_WSIZE, x)
182-
#define EX_SP_WSIZE(x) BFIN_EXTRACT(SP_WSIZE, x)
183-
184-
/* SPORT_MCMC2 Masks */
185-
#define MCCRM 0x0003 /* Multichannel Clock Recovery Mode */
186-
#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
187-
#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
188-
#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
189-
#define MCDTXPE 0x0004 /* Multichannel DMA Transmit Packing */
190-
#define MCDRXPE 0x0008 /* Multichannel DMA Receive Packing */
191-
#define MCMEN 0x0010 /* Multichannel Frame Mode Enable */
192-
#define FSDR 0x0080 /* Multichannel Frame Sync to Data Relationship */
193-
#define MFD 0xF000 /* Multichannel Frame Delay */
194-
#define DP_MFD(x) BFIN_DEPOSIT(MFD, x)
195-
#define EX_MFD(x) BFIN_EXTRACT(MFD, x)
196-
197-
#endif

‎arch/blackfin/include/asm/bfin_twi.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -61,7 +61,7 @@ struct bfin_twi_iface {
6161
int cur_msg;
6262
u16 saved_clkdiv;
6363
u16 saved_control;
64-
struct bfin_twi_regs *regs_base;
64+
struct bfin_twi_regs __iomem *regs_base;
6565
};
6666

6767
#define DEFINE_TWI_REG(reg_name, reg) \

‎arch/blackfin/include/asm/fixed_code.h

Lines changed: 2 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -6,11 +6,11 @@
66
*
77
* Licensed under the GPL-2 or later.
88
*/
9-
109
#ifndef __BFIN_ASM_FIXED_CODE_H__
1110
#define __BFIN_ASM_FIXED_CODE_H__
1211

13-
#ifdef __KERNEL__
12+
#include <uapi/asm/fixed_code.h>
13+
1414
#ifndef __ASSEMBLY__
1515
#include <linux/linkage.h>
1616
#include <linux/ptrace.h>
@@ -28,29 +28,3 @@ extern void safe_user_instruction(void);
2828
extern void sigreturn_stub(void);
2929
#endif
3030
#endif
31-
32-
#ifndef CONFIG_PHY_RAM_BASE_ADDRESS
33-
#define CONFIG_PHY_RAM_BASE_ADDRESS 0x0
34-
#endif
35-
36-
#define FIXED_CODE_START (CONFIG_PHY_RAM_BASE_ADDRESS + 0x400)
37-
38-
#define SIGRETURN_STUB (CONFIG_PHY_RAM_BASE_ADDRESS + 0x400)
39-
40-
#define ATOMIC_SEQS_START (CONFIG_PHY_RAM_BASE_ADDRESS + 0x410)
41-
42-
#define ATOMIC_XCHG32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x410)
43-
#define ATOMIC_CAS32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x420)
44-
#define ATOMIC_ADD32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x430)
45-
#define ATOMIC_SUB32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x440)
46-
#define ATOMIC_IOR32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x450)
47-
#define ATOMIC_AND32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x460)
48-
#define ATOMIC_XOR32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x470)
49-
50-
#define ATOMIC_SEQS_END (CONFIG_PHY_RAM_BASE_ADDRESS + 0x480)
51-
52-
#define SAFE_USER_INSTRUCTION (CONFIG_PHY_RAM_BASE_ADDRESS + 0x480)
53-
54-
#define FIXED_CODE_END (CONFIG_PHY_RAM_BASE_ADDRESS + 0x490)
55-
56-
#endif

‎arch/blackfin/include/asm/kvm_para.h

Lines changed: 0 additions & 1 deletion
This file was deleted.

‎arch/blackfin/include/asm/pgtable.h

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -83,8 +83,6 @@ PTE_BIT_FUNC(mkyoung, |= _PAGE_ACCESSED);
8383
#define ZERO_PAGE(vaddr) virt_to_page(empty_zero_page)
8484
extern char empty_zero_page[];
8585

86-
extern unsigned int kobjsize(const void *objp);
87-
8886
#define swapper_pg_dir ((pgd_t *) 0)
8987
/*
9088
* No page table caches to initialise.

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