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PCI: dwc: all: Split struct pcie_port into host-only and core structures
Keep only the host-specific members in struct pcie_port and move the common members (i.e common to both host and endpoint) to struct dw_pcie. This is in preparation for adding endpoint mode support to designware driver. While at that also fix checkpatch warnings. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: Jingoo Han <jingoohan1@gmail.com> CC: Richard Zhu <hongxing.zhu@nxp.com> CC: Lucas Stach <l.stach@pengutronix.de> CC: Murali Karicheri <m-karicheri2@ti.com> CC: Minghuan Lian <minghuan.Lian@freescale.com> CC: Mingkai Hu <mingkai.hu@freescale.com> CC: Roy Zang <tie-fei.zang@freescale.com> CC: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> CC: Niklas Cassel <niklas.cassel@axis.com> CC: Jesper Nilsson <jesper.nilsson@axis.com> CC: Joao Pinto <Joao.Pinto@synopsys.com> CC: Zhou Wang <wangzhou1@hisilicon.com> CC: Gabriele Paoloni <gabriele.paoloni@huawei.com> CC: Stanimir Varbanov <svarbanov@mm-sol.com> CC: Pratyush Anand <pratyush.anand@gmail.com>
1 parent 40f67fb commit 442ec4c

15 files changed

+666
-481
lines changed

‎drivers/pci/dwc/pci-dra7xx.c

Lines changed: 48 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -67,15 +67,15 @@
6767
#define EXP_CAP_ID_OFFSET 0x70
6868

6969
struct dra7xx_pcie {
70-
struct pcie_port pp;
70+
struct dw_pcie *pci;
7171
void __iomem *base; /* DT ti_conf */
7272
int phy_count; /* DT phy-names count */
7373
struct phy **phy;
7474
int link_gen;
7575
struct irq_domain *irq_domain;
7676
};
7777

78-
#define to_dra7xx_pcie(x) container_of((x), struct dra7xx_pcie, pp)
78+
#define to_dra7xx_pcie(x) dev_get_drvdata((x)->dev)
7979

8080
static inline u32 dra7xx_pcie_readl(struct dra7xx_pcie *pcie, u32 offset)
8181
{
@@ -88,42 +88,42 @@ static inline void dra7xx_pcie_writel(struct dra7xx_pcie *pcie, u32 offset,
8888
writel(value, pcie->base + offset);
8989
}
9090

91-
static int dra7xx_pcie_link_up(struct pcie_port *pp)
91+
static int dra7xx_pcie_link_up(struct dw_pcie *pci)
9292
{
93-
struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);
93+
struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
9494
u32 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_PHY_CS);
9595

9696
return !!(reg & LINK_UP);
9797
}
9898

9999
static int dra7xx_pcie_establish_link(struct dra7xx_pcie *dra7xx)
100100
{
101-
struct pcie_port *pp = &dra7xx->pp;
102-
struct device *dev = pp->dev;
101+
struct dw_pcie *pci = dra7xx->pci;
102+
struct device *dev = pci->dev;
103103
u32 reg;
104104
u32 exp_cap_off = EXP_CAP_ID_OFFSET;
105105

106-
if (dw_pcie_link_up(pp)) {
106+
if (dw_pcie_link_up(pci)) {
107107
dev_err(dev, "link is already up\n");
108108
return 0;
109109
}
110110

111111
if (dra7xx->link_gen == 1) {
112-
dw_pcie_read(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCAP,
112+
dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCAP,
113113
4, &reg);
114114
if ((reg & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
115115
reg &= ~((u32)PCI_EXP_LNKCAP_SLS);
116116
reg |= PCI_EXP_LNKCAP_SLS_2_5GB;
117-
dw_pcie_write(pp->dbi_base + exp_cap_off +
117+
dw_pcie_write(pci->dbi_base + exp_cap_off +
118118
PCI_EXP_LNKCAP, 4, reg);
119119
}
120120

121-
dw_pcie_read(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2,
121+
dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2,
122122
2, &reg);
123123
if ((reg & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
124124
reg &= ~((u32)PCI_EXP_LNKCAP_SLS);
125125
reg |= PCI_EXP_LNKCAP_SLS_2_5GB;
126-
dw_pcie_write(pp->dbi_base + exp_cap_off +
126+
dw_pcie_write(pci->dbi_base + exp_cap_off +
127127
PCI_EXP_LNKCTL2, 2, reg);
128128
}
129129
}
@@ -132,7 +132,7 @@ static int dra7xx_pcie_establish_link(struct dra7xx_pcie *dra7xx)
132132
reg |= LTSSM_EN;
133133
dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
134134

135-
return dw_pcie_wait_for_link(pp);
135+
return dw_pcie_wait_for_link(pci);
136136
}
137137

138138
static void dra7xx_pcie_enable_interrupts(struct dra7xx_pcie *dra7xx)
@@ -149,7 +149,8 @@ static void dra7xx_pcie_enable_interrupts(struct dra7xx_pcie *dra7xx)
149149

150150
static void dra7xx_pcie_host_init(struct pcie_port *pp)
151151
{
152-
struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);
152+
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
153+
struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
153154

154155
pp->io_base &= DRA7XX_CPU_TO_BUS_ADDR;
155156
pp->mem_base &= DRA7XX_CPU_TO_BUS_ADDR;
@@ -163,8 +164,7 @@ static void dra7xx_pcie_host_init(struct pcie_port *pp)
163164
dra7xx_pcie_enable_interrupts(dra7xx);
164165
}
165166

166-
static struct pcie_host_ops dra7xx_pcie_host_ops = {
167-
.link_up = dra7xx_pcie_link_up,
167+
static struct dw_pcie_host_ops dra7xx_pcie_host_ops = {
168168
.host_init = dra7xx_pcie_host_init,
169169
};
170170

@@ -183,8 +183,9 @@ static const struct irq_domain_ops intx_domain_ops = {
183183

184184
static int dra7xx_pcie_init_irq_domain(struct pcie_port *pp)
185185
{
186-
struct device *dev = pp->dev;
187-
struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);
186+
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
187+
struct device *dev = pci->dev;
188+
struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
188189
struct device_node *node = dev->of_node;
189190
struct device_node *pcie_intc_node = of_get_next_child(node, NULL);
190191

@@ -206,7 +207,8 @@ static int dra7xx_pcie_init_irq_domain(struct pcie_port *pp)
206207
static irqreturn_t dra7xx_pcie_msi_irq_handler(int irq, void *arg)
207208
{
208209
struct dra7xx_pcie *dra7xx = arg;
209-
struct pcie_port *pp = &dra7xx->pp;
210+
struct dw_pcie *pci = dra7xx->pci;
211+
struct pcie_port *pp = &pci->pp;
210212
u32 reg;
211213

212214
reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI);
@@ -233,7 +235,8 @@ static irqreturn_t dra7xx_pcie_msi_irq_handler(int irq, void *arg)
233235
static irqreturn_t dra7xx_pcie_irq_handler(int irq, void *arg)
234236
{
235237
struct dra7xx_pcie *dra7xx = arg;
236-
struct device *dev = dra7xx->pp.dev;
238+
struct dw_pcie *pci = dra7xx->pci;
239+
struct device *dev = pci->dev;
237240
u32 reg;
238241

239242
reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN);
@@ -288,8 +291,9 @@ static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx,
288291
struct platform_device *pdev)
289292
{
290293
int ret;
291-
struct pcie_port *pp = &dra7xx->pp;
292-
struct device *dev = pp->dev;
294+
struct dw_pcie *pci = dra7xx->pci;
295+
struct pcie_port *pp = &pci->pp;
296+
struct device *dev = pci->dev;
293297
struct resource *res;
294298

295299
pp->irq = platform_get_irq(pdev, 1);
@@ -311,8 +315,8 @@ static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx,
311315
return ret;
312316

313317
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rc_dbics");
314-
pp->dbi_base = devm_ioremap(dev, res->start, resource_size(res));
315-
if (!pp->dbi_base)
318+
pci->dbi_base = devm_ioremap(dev, res->start, resource_size(res));
319+
if (!pci->dbi_base)
316320
return -ENOMEM;
317321

318322
ret = dw_pcie_host_init(pp);
@@ -324,6 +328,10 @@ static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx,
324328
return 0;
325329
}
326330

331+
static const struct dw_pcie_ops dw_pcie_ops = {
332+
.link_up = dra7xx_pcie_link_up,
333+
};
334+
327335
static void dra7xx_pcie_disable_phy(struct dra7xx_pcie *dra7xx)
328336
{
329337
int phy_count = dra7xx->phy_count;
@@ -373,8 +381,9 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
373381
struct phy **phy;
374382
void __iomem *base;
375383
struct resource *res;
376-
struct dra7xx_pcie *dra7xx;
384+
struct dw_pcie *pci;
377385
struct pcie_port *pp;
386+
struct dra7xx_pcie *dra7xx;
378387
struct device *dev = &pdev->dev;
379388
struct device_node *np = dev->of_node;
380389
char name[10];
@@ -384,8 +393,14 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
384393
if (!dra7xx)
385394
return -ENOMEM;
386395

387-
pp = &dra7xx->pp;
388-
pp->dev = dev;
396+
pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
397+
if (!pci)
398+
return -ENOMEM;
399+
400+
pci->dev = dev;
401+
pci->ops = &dw_pcie_ops;
402+
403+
pp = &pci->pp;
389404
pp->ops = &dra7xx_pcie_host_ops;
390405

391406
irq = platform_get_irq(pdev, 0);
@@ -425,6 +440,7 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
425440

426441
dra7xx->base = base;
427442
dra7xx->phy = phy;
443+
dra7xx->pci = pci;
428444
dra7xx->phy_count = phy_count;
429445

430446
ret = dra7xx_pcie_enable_phy(dra7xx);
@@ -477,27 +493,27 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
477493
static int dra7xx_pcie_suspend(struct device *dev)
478494
{
479495
struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
480-
struct pcie_port *pp = &dra7xx->pp;
496+
struct dw_pcie *pci = dra7xx->pci;
481497
u32 val;
482498

483499
/* clear MSE */
484-
val = dw_pcie_readl_rc(pp, PCI_COMMAND);
500+
val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
485501
val &= ~PCI_COMMAND_MEMORY;
486-
dw_pcie_writel_rc(pp, PCI_COMMAND, val);
502+
dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
487503

488504
return 0;
489505
}
490506

491507
static int dra7xx_pcie_resume(struct device *dev)
492508
{
493509
struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
494-
struct pcie_port *pp = &dra7xx->pp;
510+
struct dw_pcie *pci = dra7xx->pci;
495511
u32 val;
496512

497513
/* set MSE */
498-
val = dw_pcie_readl_rc(pp, PCI_COMMAND);
514+
val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
499515
val |= PCI_COMMAND_MEMORY;
500-
dw_pcie_writel_rc(pp, PCI_COMMAND, val);
516+
dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
501517

502518
return 0;
503519
}

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