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bjorn-helgaasbjorn-helgaas
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PCI: designware: Return data directly from dw_pcie_readl_rc()
dw_pcie_readl_rc() reads a u32 value. Previously we stored that value in space supplied by the caller. Return the u32 value directly instead. This makes the calling code read better and makes it obvious that the caller need not initialize the storage. In the following example it isn't clear whether "val" is initialized before being used: dw_pcie_readl_rc(pp, PCI_COMMAND, &val); if (val & PCI_COMMAND_MEMORY) ... No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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3 files changed

+17
-15
lines changed

3 files changed

+17
-15
lines changed

‎drivers/pci/host/pci-exynos.c

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -425,12 +425,15 @@ static void exynos_pcie_enable_interrupts(struct pcie_port *pp)
425425
exynos_pcie_msi_init(pp);
426426
}
427427

428-
static inline void exynos_pcie_readl_rc(struct pcie_port *pp,
429-
void __iomem *dbi_base, u32 *val)
428+
static inline u32 exynos_pcie_readl_rc(struct pcie_port *pp,
429+
void __iomem *dbi_base)
430430
{
431+
u32 val;
432+
431433
exynos_pcie_sideband_dbi_r_mode(pp, true);
432-
*val = readl(dbi_base);
434+
val = readl(dbi_base);
433435
exynos_pcie_sideband_dbi_r_mode(pp, false);
436+
return val;
434437
}
435438

436439
static inline void exynos_pcie_writel_rc(struct pcie_port *pp,

‎drivers/pci/host/pcie-designware.c

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -115,12 +115,12 @@ int dw_pcie_cfg_write(void __iomem *addr, int size, u32 val)
115115
return PCIBIOS_SUCCESSFUL;
116116
}
117117

118-
static inline void dw_pcie_readl_rc(struct pcie_port *pp, u32 reg, u32 *val)
118+
static inline u32 dw_pcie_readl_rc(struct pcie_port *pp, u32 reg)
119119
{
120120
if (pp->ops->readl_rc)
121-
pp->ops->readl_rc(pp, pp->dbi_base + reg, val);
122-
else
123-
*val = readl(pp->dbi_base + reg);
121+
return pp->ops->readl_rc(pp, pp->dbi_base + reg);
122+
123+
return readl(pp->dbi_base + reg);
124124
}
125125

126126
static inline void dw_pcie_writel_rc(struct pcie_port *pp, u32 val, u32 reg)
@@ -169,7 +169,7 @@ static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index,
169169
* Make sure ATU enable takes effect before any subsequent config
170170
* and I/O accesses.
171171
*/
172-
dw_pcie_readl_rc(pp, PCIE_ATU_CR2, &val);
172+
val = dw_pcie_readl_rc(pp, PCIE_ATU_CR2);
173173
}
174174

175175
static struct irq_chip dw_msi_irq_chip = {
@@ -720,7 +720,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
720720
u32 val;
721721

722722
/* set the number of lanes */
723-
dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val);
723+
val = dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL);
724724
val &= ~PORT_LINK_MODE_MASK;
725725
switch (pp->lanes) {
726726
case 1:
@@ -742,7 +742,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
742742
dw_pcie_writel_rc(pp, val, PCIE_PORT_LINK_CONTROL);
743743

744744
/* set link width speed control register */
745-
dw_pcie_readl_rc(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, &val);
745+
val = dw_pcie_readl_rc(pp, PCIE_LINK_WIDTH_SPEED_CONTROL);
746746
val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
747747
switch (pp->lanes) {
748748
case 1:
@@ -765,19 +765,19 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
765765
dw_pcie_writel_rc(pp, 0x00000000, PCI_BASE_ADDRESS_1);
766766

767767
/* setup interrupt pins */
768-
dw_pcie_readl_rc(pp, PCI_INTERRUPT_LINE, &val);
768+
val = dw_pcie_readl_rc(pp, PCI_INTERRUPT_LINE);
769769
val &= 0xffff00ff;
770770
val |= 0x00000100;
771771
dw_pcie_writel_rc(pp, val, PCI_INTERRUPT_LINE);
772772

773773
/* setup bus numbers */
774-
dw_pcie_readl_rc(pp, PCI_PRIMARY_BUS, &val);
774+
val = dw_pcie_readl_rc(pp, PCI_PRIMARY_BUS);
775775
val &= 0xff000000;
776776
val |= 0x00010100;
777777
dw_pcie_writel_rc(pp, val, PCI_PRIMARY_BUS);
778778

779779
/* setup command register */
780-
dw_pcie_readl_rc(pp, PCI_COMMAND, &val);
780+
val = dw_pcie_readl_rc(pp, PCI_COMMAND);
781781
val &= 0xffff0000;
782782
val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
783783
PCI_COMMAND_MASTER | PCI_COMMAND_SERR;

‎drivers/pci/host/pcie-designware.h

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -57,8 +57,7 @@ struct pcie_port {
5757
};
5858

5959
struct pcie_host_ops {
60-
void (*readl_rc)(struct pcie_port *pp,
61-
void __iomem *dbi_base, u32 *val);
60+
u32 (*readl_rc)(struct pcie_port *pp, void __iomem *dbi_base);
6261
void (*writel_rc)(struct pcie_port *pp,
6362
u32 val, void __iomem *dbi_base);
6463
int (*rd_own_conf)(struct pcie_port *pp, int where, int size, u32 *val);

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