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Merge branch 'x86-intel-mid-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull Intel MID updates from Ingo Molnar: "This tree improves Intel MID (Mobile Internet Device) platform support: - Merrifield platform support (David Cohen) - Clovertrail platform support (Kuppuswamy Sathyanarayanan) - Various cleanups and fixes (David Cohen)" * 'x86-intel-mid-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86, intel_mid: Replace memcpy with struct assignment x86, intel-mid: Return proper error code from get_gpio_by_name() x86, intel-mid: Check get_gpio_by_name() error code on platform code x86, intel-mid: sfi_handle_*_dev() should check for pdata error code x86, intel-mid: Remove deprecated X86_MDFLD and X86_WANT_INTEL_MID configs x86, intel-mid: Add Merrifield platform support x86, intel-mid: Add Clovertrail platform support x86, intel-mid: Move Medfield code out of intel-mid.c core file
2 parents 972d5e7 + ee87c75 commit 4500cf6

16 files changed

+340
-75
lines changed

‎arch/x86/Kconfig

Lines changed: 7 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -439,42 +439,26 @@ config X86_INTEL_CE
439439
This option compiles in support for the CE4100 SOC for settop
440440
boxes and media devices.
441441

442-
config X86_WANT_INTEL_MID
442+
config X86_INTEL_MID
443443
bool "Intel MID platform support"
444444
depends on X86_32
445445
depends on X86_EXTENDED_PLATFORM
446-
---help---
447-
Select to build a kernel capable of supporting Intel MID platform
448-
systems which do not have the PCI legacy interfaces (Moorestown,
449-
Medfield). If you are building for a PC class system say N here.
450-
451-
if X86_WANT_INTEL_MID
452-
453-
config X86_INTEL_MID
454-
bool
455-
456-
config X86_MDFLD
457-
bool "Medfield MID platform"
458446
depends on PCI
459447
depends on PCI_GOANY
460448
depends on X86_IO_APIC
461-
select X86_INTEL_MID
462449
select SFI
450+
select I2C
463451
select DW_APB_TIMER
464452
select APB_TIMER
465-
select I2C
466-
select SPI
467453
select INTEL_SCU_IPC
468-
select X86_PLATFORM_DEVICES
469454
select MFD_INTEL_MSIC
470455
---help---
471-
Medfield is Intel's Low Power Intel Architecture (LPIA) based Moblin
472-
Internet Device(MID) platform.
473-
Unlike standard x86 PCs, Medfield does not have many legacy devices
474-
nor standard legacy replacement devices/features. e.g. Medfield does
475-
not contain i8259, i8254, HPET, legacy BIOS, most of the io ports.
456+
Select to build a kernel capable of supporting Intel MID (Mobile
457+
Internet Device) platform systems which do not have the PCI legacy
458+
interfaces. If you are building for a PC class system say N here.
476459

477-
endif
460+
Intel MID platforms are based on an Intel processor and chipset which
461+
consume less power than most of the x86 derivatives.
478462

479463
config X86_INTEL_LPSS
480464
bool "Intel Low Power Subsystem Support"

‎arch/x86/include/asm/intel-mid.h

Lines changed: 46 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -51,10 +51,41 @@ struct devs_id {
5151
enum intel_mid_cpu_type {
5252
/* 1 was Moorestown */
5353
INTEL_MID_CPU_CHIP_PENWELL = 2,
54+
INTEL_MID_CPU_CHIP_CLOVERVIEW,
55+
INTEL_MID_CPU_CHIP_TANGIER,
5456
};
5557

5658
extern enum intel_mid_cpu_type __intel_mid_cpu_chip;
5759

60+
/**
61+
* struct intel_mid_ops - Interface between intel-mid & sub archs
62+
* @arch_setup: arch_setup function to re-initialize platform
63+
* structures (x86_init, x86_platform_init)
64+
*
65+
* This structure can be extended if any new interface is required
66+
* between intel-mid & its sub arch files.
67+
*/
68+
struct intel_mid_ops {
69+
void (*arch_setup)(void);
70+
};
71+
72+
/* Helper API's for INTEL_MID_OPS_INIT */
73+
#define DECLARE_INTEL_MID_OPS_INIT(cpuname, cpuid) \
74+
[cpuid] = get_##cpuname##_ops
75+
76+
/* Maximum number of CPU ops */
77+
#define MAX_CPU_OPS(a) (sizeof(a)/sizeof(void *))
78+
79+
/*
80+
* For every new cpu addition, a weak get_<cpuname>_ops() function needs be
81+
* declared in arch/x86/platform/intel_mid/intel_mid_weak_decls.h.
82+
*/
83+
#define INTEL_MID_OPS_INIT {\
84+
DECLARE_INTEL_MID_OPS_INIT(penwell, INTEL_MID_CPU_CHIP_PENWELL), \
85+
DECLARE_INTEL_MID_OPS_INIT(cloverview, INTEL_MID_CPU_CHIP_CLOVERVIEW), \
86+
DECLARE_INTEL_MID_OPS_INIT(tangier, INTEL_MID_CPU_CHIP_TANGIER) \
87+
};
88+
5889
#ifdef CONFIG_X86_INTEL_MID
5990

6091
static inline enum intel_mid_cpu_type intel_mid_identify_cpu(void)
@@ -86,8 +117,21 @@ extern enum intel_mid_timer_options intel_mid_timer_options;
86117
* Penwell uses spread spectrum clock, so the freq number is not exactly
87118
* the same as reported by MSR based on SDM.
88119
*/
89-
#define PENWELL_FSB_FREQ_83SKU 83200
90-
#define PENWELL_FSB_FREQ_100SKU 99840
120+
#define FSB_FREQ_83SKU 83200
121+
#define FSB_FREQ_100SKU 99840
122+
#define FSB_FREQ_133SKU 133000
123+
124+
#define FSB_FREQ_167SKU 167000
125+
#define FSB_FREQ_200SKU 200000
126+
#define FSB_FREQ_267SKU 267000
127+
#define FSB_FREQ_333SKU 333000
128+
#define FSB_FREQ_400SKU 400000
129+
130+
/* Bus Select SoC Fuse value */
131+
#define BSEL_SOC_FUSE_MASK 0x7
132+
#define BSEL_SOC_FUSE_001 0x1 /* FSB 133MHz */
133+
#define BSEL_SOC_FUSE_101 0x5 /* FSB 100MHz */
134+
#define BSEL_SOC_FUSE_111 0x7 /* FSB 83MHz */
91135

92136
#define SFI_MTMR_MAX_NUM 8
93137
#define SFI_MRTC_MAX 8

‎arch/x86/pci/intel_mid_pci.c

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -31,6 +31,7 @@
3131
#include <asm/pci_x86.h>
3232
#include <asm/hw_irq.h>
3333
#include <asm/io_apic.h>
34+
#include <asm/intel-mid.h>
3435

3536
#define PCIE_CAP_OFFSET 0x100
3637

@@ -219,7 +220,10 @@ static int intel_mid_pci_irq_enable(struct pci_dev *dev)
219220
irq_attr.ioapic = mp_find_ioapic(dev->irq);
220221
irq_attr.ioapic_pin = dev->irq;
221222
irq_attr.trigger = 1; /* level */
222-
irq_attr.polarity = 1; /* active low */
223+
if (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_TANGIER)
224+
irq_attr.polarity = 0; /* active high */
225+
else
226+
irq_attr.polarity = 1; /* active low */
223227
io_apic_set_pci_routing(&dev->dev, dev->irq, &irq_attr);
224228

225229
return 0;

‎arch/x86/platform/intel-mid/Makefile

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
1-
obj-$(CONFIG_X86_INTEL_MID) += intel-mid.o
2-
obj-$(CONFIG_X86_INTEL_MID) += intel_mid_vrtc.o
1+
obj-$(CONFIG_X86_INTEL_MID) += intel-mid.o intel_mid_vrtc.o mfld.o mrfl.o
32
obj-$(CONFIG_EARLY_PRINTK_INTEL_MID) += early_printk_intel_mid.o
3+
44
# SFI specific code
55
ifdef CONFIG_X86_INTEL_MID
66
obj-$(CONFIG_SFI) += sfi.o device_libs/

‎arch/x86/platform/intel-mid/device_libs/platform_emc1403.c

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,9 @@ static void __init *emc1403_platform_data(void *info)
2222
int intr = get_gpio_by_name("thermal_int");
2323
int intr2nd = get_gpio_by_name("thermal_alert");
2424

25-
if (intr == -1 || intr2nd == -1)
25+
if (intr < 0)
26+
return NULL;
27+
if (intr2nd < 0)
2628
return NULL;
2729

2830
i2c_info->irq = intr + INTEL_MID_IRQ_OFFSET;

‎arch/x86/platform/intel-mid/device_libs/platform_gpio_keys.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -66,7 +66,7 @@ static int __init pb_keys_init(void)
6666
gb[i].gpio = get_gpio_by_name(gb[i].desc);
6767
pr_debug("info[%2d]: name = %s, gpio = %d\n", i, gb[i].desc,
6868
gb[i].gpio);
69-
if (gb[i].gpio == -1)
69+
if (gb[i].gpio < 0)
7070
continue;
7171

7272
if (i != good)

‎arch/x86/platform/intel-mid/device_libs/platform_lis331.c

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,9 @@ static void __init *lis331dl_platform_data(void *info)
2121
int intr = get_gpio_by_name("accel_int");
2222
int intr2nd = get_gpio_by_name("accel_2");
2323

24-
if (intr == -1 || intr2nd == -1)
24+
if (intr < 0)
25+
return NULL;
26+
if (intr2nd < 0)
2527
return NULL;
2628

2729
i2c_info->irq = intr + INTEL_MID_IRQ_OFFSET;

‎arch/x86/platform/intel-mid/device_libs/platform_max7315.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -48,7 +48,7 @@ static void __init *max7315_platform_data(void *info)
4848
gpio_base = get_gpio_by_name(base_pin_name);
4949
intr = get_gpio_by_name(intr_pin_name);
5050

51-
if (gpio_base == -1)
51+
if (gpio_base < 0)
5252
return NULL;
5353
max7315->gpio_base = gpio_base;
5454
if (intr != -1) {

‎arch/x86/platform/intel-mid/device_libs/platform_mpu3050.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@ static void *mpu3050_platform_data(void *info)
1919
struct i2c_board_info *i2c_info = info;
2020
int intr = get_gpio_by_name("mpu3050_int");
2121

22-
if (intr == -1)
22+
if (intr < 0)
2323
return NULL;
2424

2525
i2c_info->irq = intr + INTEL_MID_IRQ_OFFSET;

‎arch/x86/platform/intel-mid/device_libs/platform_pmic_gpio.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,7 @@ static void __init *pmic_gpio_platform_data(void *info)
2626
static struct intel_pmic_gpio_platform_data pmic_gpio_pdata;
2727
int gpio_base = get_gpio_by_name("pmic_gpio_base");
2828

29-
if (gpio_base == -1)
29+
if (gpio_base < 0)
3030
gpio_base = 64;
3131
pmic_gpio_pdata.gpio_base = gpio_base;
3232
pmic_gpio_pdata.irq_base = gpio_base + INTEL_MID_IRQ_OFFSET;

‎arch/x86/platform/intel-mid/device_libs/platform_tca6416.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -34,10 +34,10 @@ static void *tca6416_platform_data(void *info)
3434
gpio_base = get_gpio_by_name(base_pin_name);
3535
intr = get_gpio_by_name(intr_pin_name);
3636

37-
if (gpio_base == -1)
37+
if (gpio_base < 0)
3838
return NULL;
3939
tca6416.gpio_base = gpio_base;
40-
if (intr != -1) {
40+
if (intr >= 0) {
4141
i2c_info->irq = intr + INTEL_MID_IRQ_OFFSET;
4242
tca6416.irq_base = gpio_base + INTEL_MID_IRQ_OFFSET;
4343
} else {

‎arch/x86/platform/intel-mid/intel-mid.c

Lines changed: 34 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -35,6 +35,8 @@
3535
#include <asm/apb_timer.h>
3636
#include <asm/reboot.h>
3737

38+
#include "intel_mid_weak_decls.h"
39+
3840
/*
3941
* the clockevent devices on Moorestown/Medfield can be APBT or LAPIC clock,
4042
* cmdline option x86_intel_mid_timer can be used to override the configuration
@@ -58,12 +60,16 @@
5860

5961
enum intel_mid_timer_options intel_mid_timer_options;
6062

63+
/* intel_mid_ops to store sub arch ops */
64+
struct intel_mid_ops *intel_mid_ops;
65+
/* getter function for sub arch ops*/
66+
static void *(*get_intel_mid_ops[])(void) = INTEL_MID_OPS_INIT;
6167
enum intel_mid_cpu_type __intel_mid_cpu_chip;
6268
EXPORT_SYMBOL_GPL(__intel_mid_cpu_chip);
6369

6470
static void intel_mid_power_off(void)
6571
{
66-
}
72+
};
6773

6874
static void intel_mid_reboot(void)
6975
{
@@ -72,32 +78,6 @@ static void intel_mid_reboot(void)
7278

7379
static unsigned long __init intel_mid_calibrate_tsc(void)
7480
{
75-
unsigned long fast_calibrate;
76-
u32 lo, hi, ratio, fsb;
77-
78-
rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
79-
pr_debug("IA32 perf status is 0x%x, 0x%0x\n", lo, hi);
80-
ratio = (hi >> 8) & 0x1f;
81-
pr_debug("ratio is %d\n", ratio);
82-
if (!ratio) {
83-
pr_err("read a zero ratio, should be incorrect!\n");
84-
pr_err("force tsc ratio to 16 ...\n");
85-
ratio = 16;
86-
}
87-
rdmsr(MSR_FSB_FREQ, lo, hi);
88-
if ((lo & 0x7) == 0x7)
89-
fsb = PENWELL_FSB_FREQ_83SKU;
90-
else
91-
fsb = PENWELL_FSB_FREQ_100SKU;
92-
fast_calibrate = ratio * fsb;
93-
pr_debug("read penwell tsc %lu khz\n", fast_calibrate);
94-
lapic_timer_frequency = fsb * 1000 / HZ;
95-
/* mark tsc clocksource as reliable */
96-
set_cpu_cap(&boot_cpu_data, X86_FEATURE_TSC_RELIABLE);
97-
98-
if (fast_calibrate)
99-
return fast_calibrate;
100-
10181
return 0;
10282
}
10383

@@ -125,13 +105,37 @@ static void __init intel_mid_time_init(void)
125105

126106
static void intel_mid_arch_setup(void)
127107
{
128-
if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 0x27)
129-
__intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_PENWELL;
130-
else {
108+
if (boot_cpu_data.x86 != 6) {
131109
pr_err("Unknown Intel MID CPU (%d:%d), default to Penwell\n",
132110
boot_cpu_data.x86, boot_cpu_data.x86_model);
133111
__intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_PENWELL;
112+
goto out;
134113
}
114+
115+
switch (boot_cpu_data.x86_model) {
116+
case 0x35:
117+
__intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_CLOVERVIEW;
118+
break;
119+
case 0x3C:
120+
case 0x4A:
121+
__intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_TANGIER;
122+
break;
123+
case 0x27:
124+
default:
125+
__intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_PENWELL;
126+
break;
127+
}
128+
129+
if (__intel_mid_cpu_chip < MAX_CPU_OPS(get_intel_mid_ops))
130+
intel_mid_ops = get_intel_mid_ops[__intel_mid_cpu_chip]();
131+
else {
132+
intel_mid_ops = get_intel_mid_ops[INTEL_MID_CPU_CHIP_PENWELL]();
133+
pr_info("ARCH: Uknown SoC, assuming PENWELL!\n");
134+
}
135+
136+
out:
137+
if (intel_mid_ops->arch_setup)
138+
intel_mid_ops->arch_setup();
135139
}
136140

137141
/* MID systems don't have i8042 controller */

‎arch/x86/platform/intel-mid/intel_mid_weak_decls.h

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,19 @@
1+
/*
2+
* intel_mid_weak_decls.h: Weak declarations of intel-mid.c
3+
*
4+
* (C) Copyright 2013 Intel Corporation
5+
*
6+
* This program is free software; you can redistribute it and/or
7+
* modify it under the terms of the GNU General Public License
8+
* as published by the Free Software Foundation; version 2
9+
* of the License.
10+
*/
11+
12+
13+
/* __attribute__((weak)) makes these declarations overridable */
14+
/* For every CPU addition a new get_<cpuname>_ops interface needs
15+
* to be added.
16+
*/
17+
extern void * __cpuinit get_penwell_ops(void) __attribute__((weak));
18+
extern void * __cpuinit get_cloverview_ops(void) __attribute__((weak));
19+
extern void * __init get_tangier_ops(void) __attribute__((weak));

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