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Merge branch 's5p-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung
* 's5p-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: ARM: S5PV310: Fix on Secondary CPU startup ARM: S5PV310: Bug fix on uclk1 and sclk_pwm ARM: S5PV310: Fix missed uart clocks ARM: S5PV310: Should be clk_sclk_apll not clk_mout_apll ARM: S5PV310: Fix on PLL setting for S5PV310 ARM: S5PV310: Add CMU block for S5PV310 Clock ARM: S5PV310: Fix on typo irqs.h of S5PV310 ARM: S5PV310: Fix on default ZRELADDR of ARCH_S5PV310 ARM: S5PV310: Fix on GPIO base addresses ARM: SAMSUNG: Fix on build warning regarding VMALLOC_END type ARM: S5P: VMALLOC_END should be unsigned long
2 parents 30c0f6a + 766211e commit 45b5bed

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14 files changed

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-62
lines changed

14 files changed

+135
-62
lines changed

‎arch/arm/Kconfig

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1622,7 +1622,8 @@ config ZRELADDR
16221622
default 0x40008000 if ARCH_STMP378X ||\
16231623
ARCH_STMP37XX ||\
16241624
ARCH_SH7372 ||\
1625-
ARCH_SH7377
1625+
ARCH_SH7377 ||\
1626+
ARCH_S5PV310
16261627
default 0x50008000 if ARCH_S3C64XX ||\
16271628
ARCH_SH7367
16281629
default 0x60008000 if ARCH_VEXPRESS

‎arch/arm/mach-s3c2410/include/mach/vmalloc.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,6 @@
1515
#ifndef __ASM_ARCH_VMALLOC_H
1616
#define __ASM_ARCH_VMALLOC_H
1717

18-
#define VMALLOC_END (0xE0000000)
18+
#define VMALLOC_END 0xE0000000UL
1919

2020
#endif /* __ASM_ARCH_VMALLOC_H */

‎arch/arm/mach-s3c64xx/include/mach/vmalloc.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,6 @@
1515
#ifndef __ASM_ARCH_VMALLOC_H
1616
#define __ASM_ARCH_VMALLOC_H
1717

18-
#define VMALLOC_END (0xE0000000)
18+
#define VMALLOC_END 0xE0000000UL
1919

2020
#endif /* __ASM_ARCH_VMALLOC_H */

‎arch/arm/mach-s5p6440/include/mach/vmalloc.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12,6 +12,6 @@
1212
#ifndef __ASM_ARCH_VMALLOC_H
1313
#define __ASM_ARCH_VMALLOC_H
1414

15-
#define VMALLOC_END (0xE0000000)
15+
#define VMALLOC_END 0xE0000000UL
1616

1717
#endif /* __ASM_ARCH_VMALLOC_H */

‎arch/arm/mach-s5p6442/include/mach/vmalloc.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12,6 +12,6 @@
1212
#ifndef __ASM_ARCH_VMALLOC_H
1313
#define __ASM_ARCH_VMALLOC_H
1414

15-
#define VMALLOC_END (0xE0000000)
15+
#define VMALLOC_END 0xE0000000UL
1616

1717
#endif /* __ASM_ARCH_VMALLOC_H */

‎arch/arm/mach-s5pv210/include/mach/vmalloc.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,6 @@
1717
#ifndef __ASM_ARCH_VMALLOC_H
1818
#define __ASM_ARCH_VMALLOC_H __FILE__
1919

20-
#define VMALLOC_END (0xE0000000)
20+
#define VMALLOC_END (0xE0000000UL)
2121

2222
#endif /* __ASM_ARCH_VMALLOC_H */

‎arch/arm/mach-s5pv310/clock.c

Lines changed: 63 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -30,6 +30,16 @@ static struct clk clk_sclk_hdmi27m = {
3030
.rate = 27000000,
3131
};
3232

33+
static int s5pv310_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
34+
{
35+
return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
36+
}
37+
38+
static int s5pv310_clk_ip_peril_ctrl(struct clk *clk, int enable)
39+
{
40+
return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
41+
}
42+
3343
/* Core list of CMU_CPU side */
3444

3545
static struct clksrc_clk clk_mout_apll = {
@@ -39,6 +49,14 @@ static struct clksrc_clk clk_mout_apll = {
3949
},
4050
.sources = &clk_src_apll,
4151
.reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
52+
};
53+
54+
static struct clksrc_clk clk_sclk_apll = {
55+
.clk = {
56+
.name = "sclk_apll",
57+
.id = -1,
58+
.parent = &clk_mout_apll.clk,
59+
},
4260
.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
4361
};
4462

@@ -61,7 +79,7 @@ static struct clksrc_clk clk_mout_mpll = {
6179
};
6280

6381
static struct clk *clkset_moutcore_list[] = {
64-
[0] = &clk_mout_apll.clk,
82+
[0] = &clk_sclk_apll.clk,
6583
[1] = &clk_mout_mpll.clk,
6684
};
6785

@@ -154,7 +172,7 @@ static struct clksrc_clk clk_pclk_dbg = {
154172

155173
static struct clk *clkset_corebus_list[] = {
156174
[0] = &clk_mout_mpll.clk,
157-
[1] = &clk_mout_apll.clk,
175+
[1] = &clk_sclk_apll.clk,
158176
};
159177

160178
static struct clksrc_sources clkset_mout_corebus = {
@@ -220,7 +238,7 @@ static struct clksrc_clk clk_pclk_acp = {
220238

221239
static struct clk *clkset_aclk_top_list[] = {
222240
[0] = &clk_mout_mpll.clk,
223-
[1] = &clk_mout_apll.clk,
241+
[1] = &clk_sclk_apll.clk,
224242
};
225243

226244
static struct clksrc_sources clkset_aclk_200 = {
@@ -321,11 +339,6 @@ static struct clksrc_clk clk_sclk_vpll = {
321339
.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
322340
};
323341

324-
static int s5pv310_clk_ip_peril_ctrl(struct clk *clk, int enable)
325-
{
326-
return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
327-
}
328-
329342
static struct clk init_clocks_disable[] = {
330343
{
331344
.name = "timers",
@@ -337,7 +350,37 @@ static struct clk init_clocks_disable[] = {
337350
};
338351

339352
static struct clk init_clocks[] = {
340-
/* Nothing here yet */
353+
{
354+
.name = "uart",
355+
.id = 0,
356+
.enable = s5pv310_clk_ip_peril_ctrl,
357+
.ctrlbit = (1 << 0),
358+
}, {
359+
.name = "uart",
360+
.id = 1,
361+
.enable = s5pv310_clk_ip_peril_ctrl,
362+
.ctrlbit = (1 << 1),
363+
}, {
364+
.name = "uart",
365+
.id = 2,
366+
.enable = s5pv310_clk_ip_peril_ctrl,
367+
.ctrlbit = (1 << 2),
368+
}, {
369+
.name = "uart",
370+
.id = 3,
371+
.enable = s5pv310_clk_ip_peril_ctrl,
372+
.ctrlbit = (1 << 3),
373+
}, {
374+
.name = "uart",
375+
.id = 4,
376+
.enable = s5pv310_clk_ip_peril_ctrl,
377+
.ctrlbit = (1 << 4),
378+
}, {
379+
.name = "uart",
380+
.id = 5,
381+
.enable = s5pv310_clk_ip_peril_ctrl,
382+
.ctrlbit = (1 << 5),
383+
}
341384
};
342385

343386
static struct clk *clkset_group_list[] = {
@@ -359,8 +402,8 @@ static struct clksrc_clk clksrcs[] = {
359402
.clk = {
360403
.name = "uclk1",
361404
.id = 0,
405+
.enable = s5pv310_clksrc_mask_peril0_ctrl,
362406
.ctrlbit = (1 << 0),
363-
.enable = s5pv310_clk_ip_peril_ctrl,
364407
},
365408
.sources = &clkset_group,
366409
.reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 },
@@ -369,8 +412,8 @@ static struct clksrc_clk clksrcs[] = {
369412
.clk = {
370413
.name = "uclk1",
371414
.id = 1,
372-
.enable = s5pv310_clk_ip_peril_ctrl,
373-
.ctrlbit = (1 << 1),
415+
.enable = s5pv310_clksrc_mask_peril0_ctrl,
416+
.ctrlbit = (1 << 4),
374417
},
375418
.sources = &clkset_group,
376419
.reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 },
@@ -379,8 +422,8 @@ static struct clksrc_clk clksrcs[] = {
379422
.clk = {
380423
.name = "uclk1",
381424
.id = 2,
382-
.enable = s5pv310_clk_ip_peril_ctrl,
383-
.ctrlbit = (1 << 2),
425+
.enable = s5pv310_clksrc_mask_peril0_ctrl,
426+
.ctrlbit = (1 << 8),
384427
},
385428
.sources = &clkset_group,
386429
.reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 },
@@ -389,8 +432,8 @@ static struct clksrc_clk clksrcs[] = {
389432
.clk = {
390433
.name = "uclk1",
391434
.id = 3,
392-
.enable = s5pv310_clk_ip_peril_ctrl,
393-
.ctrlbit = (1 << 3),
435+
.enable = s5pv310_clksrc_mask_peril0_ctrl,
436+
.ctrlbit = (1 << 12),
394437
},
395438
.sources = &clkset_group,
396439
.reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 },
@@ -399,7 +442,7 @@ static struct clksrc_clk clksrcs[] = {
399442
.clk = {
400443
.name = "sclk_pwm",
401444
.id = -1,
402-
.enable = s5pv310_clk_ip_peril_ctrl,
445+
.enable = s5pv310_clksrc_mask_peril0_ctrl,
403446
.ctrlbit = (1 << 24),
404447
},
405448
.sources = &clkset_group,
@@ -411,6 +454,7 @@ static struct clksrc_clk clksrcs[] = {
411454
/* Clock initialization code */
412455
static struct clksrc_clk *sysclks[] = {
413456
&clk_mout_apll,
457+
&clk_sclk_apll,
414458
&clk_mout_epll,
415459
&clk_mout_mpll,
416460
&clk_moutcore,
@@ -470,11 +514,11 @@ void __init_or_cpufreq s5pv310_setup_clocks(void)
470514
apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0), pll_4508);
471515
mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0), pll_4508);
472516
epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0),
473-
__raw_readl(S5P_EPLL_CON1), pll_4500);
517+
__raw_readl(S5P_EPLL_CON1), pll_4600);
474518

475519
vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
476520
vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
477-
__raw_readl(S5P_VPLL_CON1), pll_4502);
521+
__raw_readl(S5P_VPLL_CON1), pll_4650);
478522

479523
clk_fout_apll.rate = apll;
480524
clk_fout_mpll.rate = mpll;

‎arch/arm/mach-s5pv310/cpu.c

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -45,6 +45,16 @@ static struct map_desc s5pv310_iodesc[] __initdata = {
4545
.pfn = __phys_to_pfn(S5PV310_PA_L2CC),
4646
.length = SZ_4K,
4747
.type = MT_DEVICE,
48+
}, {
49+
.virtual = (unsigned long)S5P_VA_SYSRAM,
50+
.pfn = __phys_to_pfn(S5PV310_PA_SYSRAM),
51+
.length = SZ_4K,
52+
.type = MT_DEVICE,
53+
}, {
54+
.virtual = (unsigned long)S5P_VA_CMU,
55+
.pfn = __phys_to_pfn(S5PV310_PA_CMU),
56+
.length = SZ_128K,
57+
.type = MT_DEVICE,
4858
},
4959
};
5060

‎arch/arm/mach-s5pv310/include/mach/irqs.h

Lines changed: 7 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -15,12 +15,14 @@
1515

1616
#include <plat/irqs.h>
1717

18-
/* Private Peripheral Interrupt */
18+
/* PPI: Private Peripheral Interrupt */
19+
1920
#define IRQ_PPI(x) S5P_IRQ(x+16)
2021

2122
#define IRQ_LOCALTIMER IRQ_PPI(13)
2223

23-
/* Shared Peripheral Interrupt */
24+
/* SPI: Shared Peripheral Interrupt */
25+
2426
#define IRQ_SPI(x) S5P_IRQ(x+32)
2527

2628
#define IRQ_EINT0 IRQ_SPI(40)
@@ -36,7 +38,7 @@
3638
#define IRQ_PCIE IRQ_SPI(50)
3739
#define IRQ_SYSTEM_TIMER IRQ_SPI(51)
3840
#define IRQ_MFC IRQ_SPI(52)
39-
#define IRQ_WTD IRQ_SPI(53)
41+
#define IRQ_WDT IRQ_SPI(53)
4042
#define IRQ_AUDIO_SS IRQ_SPI(54)
4143
#define IRQ_AC97 IRQ_SPI(55)
4244
#define IRQ_SPDIF IRQ_SPI(56)
@@ -67,8 +69,9 @@
6769
#define IRQ_IIC COMBINER_IRQ(27, 0)
6870

6971
/* Set the default NR_IRQS */
72+
7073
#define NR_IRQS COMBINER_IRQ(MAX_COMBINER_NR, 0)
7174

7275
#define MAX_COMBINER_NR 39
7376

74-
#endif /* ASM_ARCH_IRQS_H */
77+
#endif /* __ASM_ARCH_IRQS_H */

‎arch/arm/mach-s5pv310/include/mach/map.h

Lines changed: 14 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -23,12 +23,16 @@
2323

2424
#include <plat/map-s5p.h>
2525

26+
#define S5PV310_PA_SYSRAM (0x02025000)
27+
2628
#define S5PV310_PA_CHIPID (0x10000000)
2729
#define S5P_PA_CHIPID S5PV310_PA_CHIPID
2830

2931
#define S5PV310_PA_SYSCON (0x10020000)
3032
#define S5P_PA_SYSCON S5PV310_PA_SYSCON
3133

34+
#define S5PV310_PA_CMU (0x10030000)
35+
3236
#define S5PV310_PA_WATCHDOG (0x10060000)
3337

3438
#define S5PV310_PA_COMBINER (0x10448000)
@@ -39,8 +43,12 @@
3943
#define S5PV310_PA_GIC_DIST (0x10501000)
4044
#define S5PV310_PA_L2CC (0x10502000)
4145

42-
#define S5PV310_PA_GPIO (0x11000000)
43-
#define S5P_PA_GPIO S5PV310_PA_GPIO
46+
#define S5PV310_PA_GPIO1 (0x11400000)
47+
#define S5PV310_PA_GPIO2 (0x11000000)
48+
#define S5PV310_PA_GPIO3 (0x03860000)
49+
#define S5P_PA_GPIO S5PV310_PA_GPIO1
50+
51+
#define S5PV310_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000))
4452

4553
#define S5PV310_PA_UART (0x13800000)
4654

@@ -63,6 +71,10 @@
6371

6472
/* compatibiltiy defines. */
6573
#define S3C_PA_UART S5PV310_PA_UART
74+
#define S3C_PA_HSMMC0 S5PV310_PA_HSMMC(0)
75+
#define S3C_PA_HSMMC1 S5PV310_PA_HSMMC(1)
76+
#define S3C_PA_HSMMC2 S5PV310_PA_HSMMC(2)
77+
#define S3C_PA_HSMMC3 S5PV310_PA_HSMMC(3)
6678
#define S3C_PA_IIC S5PV310_PA_IIC0
6779
#define S3C_PA_WDT S5PV310_PA_WATCHDOG
6880

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