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Merge tag 'irqchip-core-4.9' of git://git.infradead.org/users/jcooper/linux into irq/core
Pull irqchip core changes for v4.9 from Jason Cooper - jcore: Add AIC driver - mips-gic: Use for_each_set_bit - mvebu: Add PIC driver
2 parents 5a79d59 + f61f860 commit 474aa3d

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‎Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt

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J-Core Advanced Interrupt Controller
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Required properties:
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- compatible: Should be "jcore,aic1" for the (obsolete) first-generation aic
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with 8 interrupt lines with programmable priorities, or "jcore,aic2" for
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the "aic2" core with 64 interrupts.
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- reg: Memory region(s) for configuration. For SMP, there should be one
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region per cpu, indexed by the sequential, zero-based hardware cpu
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number.
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- interrupt-controller: Identifies the node as an interrupt controller
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- #interrupt-cells: Specifies the number of cells needed to encode an
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interrupt source. The value shall be 1.
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18+
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Example:
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aic: interrupt-controller@200 {
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compatible = "jcore,aic2";
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reg = < 0x200 0x30 0x500 0x30 >;
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interrupt-controller;
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#interrupt-cells = <1>;
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};

‎Documentation/devicetree/bindings/interrupt-controller/marvell,armada-8k-pic.txt

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Marvell Armada 7K/8K PIC Interrupt controller
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---------------------------------------------
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This is the Device Tree binding for the PIC, a secondary interrupt
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controller available on the Marvell Armada 7K/8K ARM64 SoCs, and
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typically connected to the GIC as the primary interrupt controller.
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Required properties:
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- compatible: should be "marvell,armada-8k-pic"
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- interrupt-controller: identifies the node as an interrupt controller
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- #interrupt-cells: the number of cells to define interrupts on this
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controller. Should be 1
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- reg: the register area for the PIC interrupt controller
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- interrupts: the interrupt to the primary interrupt controller,
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typically the GIC
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Example:
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pic: interrupt-controller@3f0100 {
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compatible = "marvell,armada-8k-pic";
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reg = <0x3f0100 0x10>;
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#interrupt-cells = <1>;
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interrupt-controller;
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interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
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};

‎Documentation/devicetree/bindings/interrupt-controller/marvell,odmi-controller.txt

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@@ -31,7 +31,7 @@ Required properties:
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Example:
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odmi: odmi@300000 {
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compatible = "marvell,ap806-odm-controller",
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compatible = "marvell,ap806-odmi-controller",
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"marvell,odmi-controller";
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interrupt-controller;
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msi-controller;

‎arch/arm64/Kconfig.platforms

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@@ -93,6 +93,7 @@ config ARCH_MVEBU
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select ARMADA_CP110_SYSCON
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select ARMADA_37XX_CLK
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select MVEBU_ODMI
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select MVEBU_PIC
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help
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This enables support for Marvell EBU familly, including:
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- Armada 3700 SoC Family

‎drivers/irqchip/Kconfig

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Original file line numberDiff line numberDiff line change
@@ -157,6 +157,13 @@ config PIC32_EVIC
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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config JCORE_AIC
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bool "J-Core integrated AIC"
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depends on OF && (SUPERH || COMPILE_TEST)
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select IRQ_DOMAIN
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help
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Support for the J-Core integrated AIC.
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160167
config RENESAS_INTC_IRQPIN
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bool
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select IRQ_DOMAIN
@@ -252,6 +259,9 @@ config IRQ_MXS
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config MVEBU_ODMI
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bool
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config MVEBU_PIC
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bool
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config LS_SCFG_MSI
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def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
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depends on PCI && PCI_MSI

‎drivers/irqchip/Makefile

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Original file line numberDiff line numberDiff line change
@@ -40,6 +40,7 @@ obj-$(CONFIG_I8259) += irq-i8259.o
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obj-$(CONFIG_IMGPDC_IRQ) += irq-imgpdc.o
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obj-$(CONFIG_IRQ_MIPS_CPU) += irq-mips-cpu.o
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obj-$(CONFIG_SIRF_IRQ) += irq-sirfsoc.o
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obj-$(CONFIG_JCORE_AIC) += irq-jcore-aic.o
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obj-$(CONFIG_RENESAS_INTC_IRQPIN) += irq-renesas-intc-irqpin.o
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obj-$(CONFIG_RENESAS_IRQC) += irq-renesas-irqc.o
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obj-$(CONFIG_VERSATILE_FPGA_IRQ) += irq-versatile-fpga.o
@@ -68,6 +69,7 @@ obj-$(CONFIG_INGENIC_IRQ) += irq-ingenic.o
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obj-$(CONFIG_IMX_GPCV2) += irq-imx-gpcv2.o
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obj-$(CONFIG_PIC32_EVIC) += irq-pic32-evic.o
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obj-$(CONFIG_MVEBU_ODMI) += irq-mvebu-odmi.o
72+
obj-$(CONFIG_MVEBU_PIC) += irq-mvebu-pic.o
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obj-$(CONFIG_LS_SCFG_MSI) += irq-ls-scfg-msi.o
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obj-$(CONFIG_EZNPS_GIC) += irq-eznps.o
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obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o

‎drivers/irqchip/irq-jcore-aic.c

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/*
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* J-Core SoC AIC driver
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*
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* Copyright (C) 2015-2016 Smart Energy Instruments, Inc.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/irqchip.h>
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#include <linux/irqdomain.h>
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#include <linux/cpu.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#define JCORE_AIC_MAX_HWIRQ 127
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#define JCORE_AIC1_MIN_HWIRQ 16
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#define JCORE_AIC2_MIN_HWIRQ 64
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24+
#define JCORE_AIC1_INTPRI_REG 8
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static struct irq_chip jcore_aic;
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28+
static int jcore_aic_irqdomain_map(struct irq_domain *d, unsigned int irq,
29+
irq_hw_number_t hwirq)
30+
{
31+
struct irq_chip *aic = d->host_data;
32+
33+
irq_set_chip_and_handler(irq, aic, handle_simple_irq);
34+
35+
return 0;
36+
}
37+
38+
static const struct irq_domain_ops jcore_aic_irqdomain_ops = {
39+
.map = jcore_aic_irqdomain_map,
40+
.xlate = irq_domain_xlate_onecell,
41+
};
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43+
static void noop(struct irq_data *data)
44+
{
45+
}
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47+
static int __init aic_irq_of_init(struct device_node *node,
48+
struct device_node *parent)
49+
{
50+
unsigned min_irq = JCORE_AIC2_MIN_HWIRQ;
51+
unsigned dom_sz = JCORE_AIC_MAX_HWIRQ+1;
52+
struct irq_domain *domain;
53+
54+
pr_info("Initializing J-Core AIC\n");
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56+
/* AIC1 needs priority initialization to receive interrupts. */
57+
if (of_device_is_compatible(node, "jcore,aic1")) {
58+
unsigned cpu;
59+
60+
for_each_present_cpu(cpu) {
61+
void __iomem *base = of_iomap(node, cpu);
62+
63+
if (!base) {
64+
pr_err("Unable to map AIC for cpu %u\n", cpu);
65+
return -ENOMEM;
66+
}
67+
__raw_writel(0xffffffff, base + JCORE_AIC1_INTPRI_REG);
68+
iounmap(base);
69+
}
70+
min_irq = JCORE_AIC1_MIN_HWIRQ;
71+
}
72+
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/*
74+
* The irq chip framework requires either mask/unmask or enable/disable
75+
* function pointers to be provided, but the hardware does not have any
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* such mechanism; the only interrupt masking is at the cpu level and
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* it affects all interrupts. We provide dummy mask/unmask. The hardware
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* handles all interrupt control and clears pending status when the cpu
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* accepts the interrupt.
80+
*/
81+
jcore_aic.irq_mask = noop;
82+
jcore_aic.irq_unmask = noop;
83+
jcore_aic.name = "AIC";
84+
85+
domain = irq_domain_add_linear(node, dom_sz, &jcore_aic_irqdomain_ops,
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&jcore_aic);
87+
if (!domain)
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return -ENOMEM;
89+
irq_create_strict_mappings(domain, min_irq, min_irq, dom_sz - min_irq);
90+
91+
return 0;
92+
}
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94+
IRQCHIP_DECLARE(jcore_aic2, "jcore,aic2", aic_irq_of_init);
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IRQCHIP_DECLARE(jcore_aic1, "jcore,aic1", aic_irq_of_init);

‎drivers/irqchip/irq-keystone.c

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@@ -109,7 +109,7 @@ static void keystone_irq_handler(struct irq_desc *desc)
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dev_dbg(kirq->dev, "dispatch bit %d, virq %d\n",
110110
src, virq);
111111
if (!virq)
112-
dev_warn(kirq->dev, "sporious irq detected hwirq %d, virq %d\n",
112+
dev_warn(kirq->dev, "spurious irq detected hwirq %d, virq %d\n",
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src, virq);
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generic_handle_irq(virq);
115115
}

‎drivers/irqchip/irq-mips-gic.c

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@@ -371,18 +371,13 @@ static void gic_handle_shared_int(bool chained)
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bitmap_and(pending, pending, intrmask, gic_shared_intrs);
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bitmap_and(pending, pending, pcpu_mask, gic_shared_intrs);
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374-
intr = find_first_bit(pending, gic_shared_intrs);
375-
while (intr != gic_shared_intrs) {
374+
for_each_set_bit(intr, pending, gic_shared_intrs) {
376375
virq = irq_linear_revmap(gic_irq_domain,
377376
GIC_SHARED_TO_HWIRQ(intr));
378377
if (chained)
379378
generic_handle_irq(virq);
380379
else
381380
do_IRQ(virq);
382-
383-
/* go to next pending bit */
384-
bitmap_clear(pending, intr, 1);
385-
intr = find_first_bit(pending, gic_shared_intrs);
386381
}
387382
}
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