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#include "init_64.h"
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unsigned long kern_linear_pte_xor [4 ] __read_mostly ;
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+ static unsigned long page_cache4v_flag ;
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/* A bitmap, two bits for every 256MB of physical memory. These two
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* bits determine what page size we use for kernel linear
@@ -1909,11 +1910,24 @@ static void __init sun4u_linear_pte_xor_finalize(void)
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static void __init sun4v_linear_pte_xor_finalize (void )
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{
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+ unsigned long pagecv_flag ;
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+
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+ /* Bit 9 of TTE is no longer CV bit on M7 processor and it instead
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+ * enables MCD error. Do not set bit 9 on M7 processor.
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+ */
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+ switch (sun4v_chip_type ) {
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+ case SUN4V_CHIP_SPARC_M7 :
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+ pagecv_flag = 0x00 ;
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+ break ;
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+ default :
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+ pagecv_flag = _PAGE_CV_4V ;
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+ break ;
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+ }
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#ifndef CONFIG_DEBUG_PAGEALLOC
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if (cpu_pgsz_mask & HV_PGSZ_MASK_256MB ) {
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kern_linear_pte_xor [1 ] = (_PAGE_VALID | _PAGE_SZ256MB_4V ) ^
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PAGE_OFFSET ;
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- kern_linear_pte_xor [1 ] |= (_PAGE_CP_4V | _PAGE_CV_4V |
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+ kern_linear_pte_xor [1 ] |= (_PAGE_CP_4V | pagecv_flag |
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_PAGE_P_4V | _PAGE_W_4V );
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} else {
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kern_linear_pte_xor [1 ] = kern_linear_pte_xor [0 ];
@@ -1922,7 +1936,7 @@ static void __init sun4v_linear_pte_xor_finalize(void)
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if (cpu_pgsz_mask & HV_PGSZ_MASK_2GB ) {
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kern_linear_pte_xor [2 ] = (_PAGE_VALID | _PAGE_SZ2GB_4V ) ^
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PAGE_OFFSET ;
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- kern_linear_pte_xor [2 ] |= (_PAGE_CP_4V | _PAGE_CV_4V |
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+ kern_linear_pte_xor [2 ] |= (_PAGE_CP_4V | pagecv_flag |
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_PAGE_P_4V | _PAGE_W_4V );
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} else {
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kern_linear_pte_xor [2 ] = kern_linear_pte_xor [1 ];
@@ -1931,7 +1945,7 @@ static void __init sun4v_linear_pte_xor_finalize(void)
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if (cpu_pgsz_mask & HV_PGSZ_MASK_16GB ) {
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kern_linear_pte_xor [3 ] = (_PAGE_VALID | _PAGE_SZ16GB_4V ) ^
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PAGE_OFFSET ;
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- kern_linear_pte_xor [3 ] |= (_PAGE_CP_4V | _PAGE_CV_4V |
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+ kern_linear_pte_xor [3 ] |= (_PAGE_CP_4V | pagecv_flag |
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_PAGE_P_4V | _PAGE_W_4V );
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} else {
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kern_linear_pte_xor [3 ] = kern_linear_pte_xor [2 ];
@@ -1958,6 +1972,13 @@ static phys_addr_t __init available_memory(void)
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return available ;
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}
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+ #define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U)
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+ #define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V)
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+ #define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
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+ #define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
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+ #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
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+ #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
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+
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/* We need to exclude reserved regions. This exclusion will include
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* vmlinux and initrd. To be more precise the initrd size could be used to
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* compute a new lower limit because it is freed later during initialization.
@@ -2034,6 +2055,25 @@ void __init paging_init(void)
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memset (swapper_4m_tsb , 0x40 , sizeof (swapper_4m_tsb ));
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#endif
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+ /* TTE.cv bit on sparc v9 occupies the same position as TTE.mcde
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+ * bit on M7 processor. This is a conflicting usage of the same
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+ * bit. Enabling TTE.cv on M7 would turn on Memory Corruption
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+ * Detection error on all pages and this will lead to problems
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+ * later. Kernel does not run with MCD enabled and hence rest
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+ * of the required steps to fully configure memory corruption
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+ * detection are not taken. We need to ensure TTE.mcde is not
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+ * set on M7 processor. Compute the value of cacheability
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+ * flag for use later taking this into consideration.
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+ */
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+ switch (sun4v_chip_type ) {
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+ case SUN4V_CHIP_SPARC_M7 :
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+ page_cache4v_flag = _PAGE_CP_4V ;
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+ break ;
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+ default :
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+ page_cache4v_flag = _PAGE_CACHE_4V ;
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+ break ;
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+ }
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+
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if (tlb_type == hypervisor )
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sun4v_pgprot_init ();
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else
@@ -2274,13 +2314,6 @@ void free_initrd_mem(unsigned long start, unsigned long end)
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}
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#endif
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- #define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U)
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- #define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V)
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- #define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
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- #define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
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- #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
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- #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
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-
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pgprot_t PAGE_KERNEL __read_mostly ;
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EXPORT_SYMBOL (PAGE_KERNEL );
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@@ -2312,8 +2345,7 @@ int __meminit vmemmap_populate(unsigned long vstart, unsigned long vend,
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_PAGE_P_4U | _PAGE_W_4U );
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if (tlb_type == hypervisor )
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pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V |
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- _PAGE_CP_4V | _PAGE_CV_4V |
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- _PAGE_P_4V | _PAGE_W_4V );
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+ page_cache4v_flag | _PAGE_P_4V | _PAGE_W_4V );
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pte_base |= _PAGE_PMD_HUGE ;
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@@ -2450,23 +2482,23 @@ static void __init sun4v_pgprot_init(void)
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int i ;
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PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
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- _PAGE_CACHE_4V | _PAGE_P_4V |
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+ page_cache4v_flag | _PAGE_P_4V |
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__ACCESS_BITS_4V | __DIRTY_BITS_4V |
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_PAGE_EXEC_4V );
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PAGE_KERNEL_LOCKED = PAGE_KERNEL ;
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_PAGE_IE = _PAGE_IE_4V ;
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_PAGE_E = _PAGE_E_4V ;
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- _PAGE_CACHE = _PAGE_CACHE_4V ;
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+ _PAGE_CACHE = page_cache4v_flag ;
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#ifdef CONFIG_DEBUG_PAGEALLOC
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kern_linear_pte_xor [0 ] = _PAGE_VALID ^ PAGE_OFFSET ;
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#else
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kern_linear_pte_xor [0 ] = (_PAGE_VALID | _PAGE_SZ4MB_4V ) ^
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PAGE_OFFSET ;
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#endif
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- kern_linear_pte_xor [0 ] |= (_PAGE_CP_4V | _PAGE_CV_4V |
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- _PAGE_P_4V | _PAGE_W_4V );
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+ kern_linear_pte_xor [0 ] |= (page_cache4v_flag | _PAGE_P_4V |
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+ _PAGE_W_4V );
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for (i = 1 ; i < 4 ; i ++ )
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kern_linear_pte_xor [i ] = kern_linear_pte_xor [0 ];
@@ -2479,12 +2511,12 @@ static void __init sun4v_pgprot_init(void)
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_PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
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_PAGE_SZ64K_4V | _PAGE_SZ8K_4V );
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- page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | _PAGE_CACHE_4V ;
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- page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
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+ page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | page_cache4v_flag ;
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+ page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
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__ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V );
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- page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
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+ page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
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__ACCESS_BITS_4V | _PAGE_EXEC_4V );
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- page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
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+ page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
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__ACCESS_BITS_4V | _PAGE_EXEC_4V );
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page_exec_bit = _PAGE_EXEC_4V ;
@@ -2542,7 +2574,7 @@ static unsigned long kern_large_tte(unsigned long paddr)
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_PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U );
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if (tlb_type == hypervisor )
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val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
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- _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_P_4V |
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+ page_cache4v_flag | _PAGE_P_4V |
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_PAGE_EXEC_4V | _PAGE_W_4V );
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return val | paddr ;
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