Skip to content

Commit 4a89cf8

Browse files
ralfbaechleralfbaechle
committed
Merge branch '4.7-fixes' into mips-for-linux-next
2 parents 4f53989 + e9cbf62 commit 4a89cf8

File tree

131 files changed

+1150
-605
lines changed

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

131 files changed

+1150
-605
lines changed

‎Documentation/x86/intel_mpx.txt

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -45,7 +45,7 @@ is how we expect the compiler, application and kernel to work together.
4545
MPX-instrumented.
4646
3) The kernel detects that the CPU has MPX, allows the new prctl() to
4747
succeed, and notes the location of the bounds directory. Userspace is
48-
expected to keep the bounds directory at that locationWe note it
48+
expected to keep the bounds directory at that location. We note it
4949
instead of reading it each time because the 'xsave' operation needed
5050
to access the bounds directory register is an expensive operation.
5151
4) If the application needs to spill bounds out of the 4 registers, it
@@ -167,7 +167,7 @@ If a #BR is generated due to a bounds violation caused by MPX.
167167
We need to decode MPX instructions to get violation address and
168168
set this address into extended struct siginfo.
169169

170-
The _sigfault feild of struct siginfo is extended as follow:
170+
The _sigfault field of struct siginfo is extended as follow:
171171

172172
87 /* SIGILL, SIGFPE, SIGSEGV, SIGBUS */
173173
88 struct {
@@ -240,5 +240,5 @@ them at the same bounds table.
240240
This is allowed architecturally. See more information "Intel(R) Architecture
241241
Instruction Set Extensions Programming Reference" (9.3.4).
242242

243-
However, if users did this, the kernel might be fooled in to unmaping an
243+
However, if users did this, the kernel might be fooled in to unmapping an
244244
in-use bounds table since it does not recognize sharing.

‎Documentation/x86/tlb.txt

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@ memory, it has two choices:
55
from areas other than the one we are trying to flush will be
66
destroyed and must be refilled later, at some cost.
77
2. Use the invlpg instruction to invalidate a single page at a
8-
time. This could potentialy cost many more instructions, but
8+
time. This could potentially cost many more instructions, but
99
it is a much more precise operation, causing no collateral
1010
damage to other TLB entries.
1111

@@ -19,7 +19,7 @@ Which method to do depends on a few things:
1919
work.
2020
3. The size of the TLB. The larger the TLB, the more collateral
2121
damage we do with a full flush. So, the larger the TLB, the
22-
more attrative an individual flush looks. Data and
22+
more attractive an individual flush looks. Data and
2323
instructions have separate TLBs, as do different page sizes.
2424
4. The microarchitecture. The TLB has become a multi-level
2525
cache on modern CPUs, and the global flushes have become more

‎Documentation/x86/x86_64/machinecheck

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -36,7 +36,7 @@ between all CPUs.
3636

3737
check_interval
3838
How often to poll for corrected machine check errors, in seconds
39-
(Note output is hexademical). Default 5 minutes. When the poller
39+
(Note output is hexadecimal). Default 5 minutes. When the poller
4040
finds MCEs it triggers an exponential speedup (poll more often) on
4141
the polling interval. When the poller stops finding MCEs, it
4242
triggers an exponential backoff (poll less often) on the polling

‎Makefile

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
VERSION = 4
22
PATCHLEVEL = 7
33
SUBLEVEL = 0
4-
EXTRAVERSION = -rc6
4+
EXTRAVERSION = -rc7
55
NAME = Psychotic Stoned Sheep
66

77
# *DOCUMENTATION*

‎arch/arm64/include/asm/cputype.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -80,12 +80,14 @@
8080
#define APM_CPU_PART_POTENZA 0x000
8181

8282
#define CAVIUM_CPU_PART_THUNDERX 0x0A1
83+
#define CAVIUM_CPU_PART_THUNDERX_81XX 0x0A2
8384

8485
#define BRCM_CPU_PART_VULCAN 0x516
8586

8687
#define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
8788
#define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
8889
#define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
90+
#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
8991

9092
#ifndef __ASSEMBLY__
9193

‎arch/arm64/include/asm/ptrace.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -117,6 +117,8 @@ struct pt_regs {
117117
};
118118
u64 orig_x0;
119119
u64 syscallno;
120+
u64 orig_addr_limit;
121+
u64 unused; // maintain 16 byte alignment
120122
};
121123

122124
#define arch_has_single_step() (1)

‎arch/arm64/kernel/asm-offsets.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -60,6 +60,7 @@ int main(void)
6060
DEFINE(S_PC, offsetof(struct pt_regs, pc));
6161
DEFINE(S_ORIG_X0, offsetof(struct pt_regs, orig_x0));
6262
DEFINE(S_SYSCALLNO, offsetof(struct pt_regs, syscallno));
63+
DEFINE(S_ORIG_ADDR_LIMIT, offsetof(struct pt_regs, orig_addr_limit));
6364
DEFINE(S_FRAME_SIZE, sizeof(struct pt_regs));
6465
BLANK();
6566
DEFINE(MM_CONTEXT_ID, offsetof(struct mm_struct, context.id.counter));

‎arch/arm64/kernel/cpu_errata.c

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -98,6 +98,12 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
9898
MIDR_RANGE(MIDR_THUNDERX, 0x00,
9999
(1 << MIDR_VARIANT_SHIFT) | 1),
100100
},
101+
{
102+
/* Cavium ThunderX, T81 pass 1.0 */
103+
.desc = "Cavium erratum 27456",
104+
.capability = ARM64_WORKAROUND_CAVIUM_27456,
105+
MIDR_RANGE(MIDR_THUNDERX_81XX, 0x00, 0x00),
106+
},
101107
#endif
102108
{
103109
}

‎arch/arm64/kernel/entry.S

Lines changed: 17 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -28,6 +28,7 @@
2828
#include <asm/errno.h>
2929
#include <asm/esr.h>
3030
#include <asm/irq.h>
31+
#include <asm/memory.h>
3132
#include <asm/thread_info.h>
3233
#include <asm/unistd.h>
3334

@@ -97,7 +98,14 @@
9798
mov x29, xzr // fp pointed to user-space
9899
.else
99100
add x21, sp, #S_FRAME_SIZE
100-
.endif
101+
get_thread_info tsk
102+
/* Save the task's original addr_limit and set USER_DS (TASK_SIZE_64) */
103+
ldr x20, [tsk, #TI_ADDR_LIMIT]
104+
str x20, [sp, #S_ORIG_ADDR_LIMIT]
105+
mov x20, #TASK_SIZE_64
106+
str x20, [tsk, #TI_ADDR_LIMIT]
107+
ALTERNATIVE(nop, SET_PSTATE_UAO(0), ARM64_HAS_UAO, CONFIG_ARM64_UAO)
108+
.endif /* \el == 0 */
101109
mrs x22, elr_el1
102110
mrs x23, spsr_el1
103111
stp lr, x21, [sp, #S_LR]
@@ -128,6 +136,14 @@
128136
.endm
129137

130138
.macro kernel_exit, el
139+
.if \el != 0
140+
/* Restore the task's original addr_limit. */
141+
ldr x20, [sp, #S_ORIG_ADDR_LIMIT]
142+
str x20, [tsk, #TI_ADDR_LIMIT]
143+
144+
/* No need to restore UAO, it will be restored from SPSR_EL1 */
145+
.endif
146+
131147
ldp x21, x22, [sp, #S_PC] // load ELR, SPSR
132148
.if \el == 0
133149
ct_user_enter
@@ -406,7 +422,6 @@ el1_irq:
406422
bl trace_hardirqs_off
407423
#endif
408424

409-
get_thread_info tsk
410425
irq_handler
411426

412427
#ifdef CONFIG_PREEMPT

‎arch/arm64/mm/fault.c

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -280,7 +280,8 @@ static int __kprobes do_page_fault(unsigned long addr, unsigned int esr,
280280
}
281281

282282
if (permission_fault(esr) && (addr < USER_DS)) {
283-
if (get_fs() == KERNEL_DS)
283+
/* regs->orig_addr_limit may be 0 if we entered from EL0 */
284+
if (regs->orig_addr_limit == KERNEL_DS)
284285
die("Accessing user space memory with fs=KERNEL_DS", regs, esr);
285286

286287
if (!search_exception_tables(regs->pc))

‎arch/mips/cavium-octeon/octeon-irq.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1260,7 +1260,7 @@ static int octeon_irq_gpio_map(struct irq_domain *d,
12601260

12611261
line = (hw + gpiod->base_hwirq) >> 6;
12621262
bit = (hw + gpiod->base_hwirq) & 63;
1263-
if (line > ARRAY_SIZE(octeon_irq_ciu_to_irq) ||
1263+
if (line >= ARRAY_SIZE(octeon_irq_ciu_to_irq) ||
12641264
octeon_irq_ciu_to_irq[line][bit] != 0)
12651265
return -EINVAL;
12661266

‎arch/mips/include/asm/msa.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -168,6 +168,7 @@ static inline unsigned int read_msa_##name(void) \
168168
unsigned int reg; \
169169
__asm__ __volatile__( \
170170
" .set push\n" \
171+
" .set fp=64\n" \
171172
" .set msa\n" \
172173
" cfcmsa %0, $" #cs "\n" \
173174
" .set pop\n" \
@@ -179,6 +180,7 @@ static inline void write_msa_##name(unsigned int val) \
179180
{ \
180181
__asm__ __volatile__( \
181182
" .set push\n" \
183+
" .set fp=64\n" \
182184
" .set msa\n" \
183185
" ctcmsa $" #cs ", %0\n" \
184186
" .set pop\n" \

‎arch/mips/kernel/cevt-r4k.c

Lines changed: 1 addition & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -276,20 +276,15 @@ int r4k_clockevent_init(void)
276276
CLOCK_EVT_FEAT_C3STOP |
277277
CLOCK_EVT_FEAT_PERCPU;
278278

279-
clockevent_set_clock(cd, mips_hpt_frequency);
280-
281-
/* Calculate the min / max delta */
282-
cd->max_delta_ns = clockevent_delta2ns(0x7fffffff, cd);
283279
min_delta = calculate_min_delta();
284-
cd->min_delta_ns = clockevent_delta2ns(min_delta, cd);
285280

286281
cd->rating = 300;
287282
cd->irq = irq;
288283
cd->cpumask = cpumask_of(cpu);
289284
cd->set_next_event = mips_next_event;
290285
cd->event_handler = mips_event_handler;
291286

292-
clockevents_register_device(cd);
287+
clockevents_config_and_register(cd, mips_hpt_frequency, min_delta, 0x7fffffff);
293288

294289
if (cp0_timer_irq_installed)
295290
return 0;

‎arch/mips/kernel/csrc-r4k.c

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -23,7 +23,7 @@ static struct clocksource clocksource_mips = {
2323
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
2424
};
2525

26-
static u64 notrace r4k_read_sched_clock(void)
26+
static u64 __maybe_unused notrace r4k_read_sched_clock(void)
2727
{
2828
return read_c0_count();
2929
}
@@ -82,7 +82,9 @@ int __init init_r4k_clocksource(void)
8282

8383
clocksource_register_hz(&clocksource_mips, mips_hpt_frequency);
8484

85+
#ifndef CONFIG_CPU_FREQ
8586
sched_clock_register(r4k_read_sched_clock, 32, mips_hpt_frequency);
87+
#endif
8688

8789
return 0;
8890
}

‎arch/mips/kernel/traps.c

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -704,6 +704,7 @@ asmlinkage void do_ov(struct pt_regs *regs)
704704
int process_fpemu_return(int sig, void __user *fault_addr, unsigned long fcr31)
705705
{
706706
struct siginfo si = { 0 };
707+
struct vm_area_struct *vma;
707708

708709
switch (sig) {
709710
case 0:
@@ -744,7 +745,8 @@ int process_fpemu_return(int sig, void __user *fault_addr, unsigned long fcr31)
744745
si.si_addr = fault_addr;
745746
si.si_signo = sig;
746747
down_read(&current->mm->mmap_sem);
747-
if (find_vma(current->mm, (unsigned long)fault_addr))
748+
vma = find_vma(current->mm, (unsigned long)fault_addr);
749+
if (vma && (vma->vm_start <= (unsigned long)fault_addr))
748750
si.si_code = SEGV_ACCERR;
749751
else
750752
si.si_code = SEGV_MAPERR;

‎arch/mips/lantiq/irq.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -344,7 +344,7 @@ static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
344344
if (hw == ltq_eiu_irq[i])
345345
chip = &ltq_eiu_type;
346346

347-
irq_set_chip_and_handler(hw, chip, handle_level_irq);
347+
irq_set_chip_and_handler(irq, chip, handle_level_irq);
348348

349349
return 0;
350350
}

‎arch/mips/loongson64/loongson-3/hpet.c

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -13,8 +13,8 @@
1313
#define SMBUS_PCI_REG64 0x64
1414
#define SMBUS_PCI_REGB4 0xb4
1515

16-
#define HPET_MIN_CYCLES 64
17-
#define HPET_MIN_PROG_DELTA (HPET_MIN_CYCLES + (HPET_MIN_CYCLES >> 1))
16+
#define HPET_MIN_CYCLES 16
17+
#define HPET_MIN_PROG_DELTA (HPET_MIN_CYCLES * 12)
1818

1919
static DEFINE_SPINLOCK(hpet_lock);
2020
DEFINE_PER_CPU(struct clock_event_device, hpet_clockevent_device);
@@ -157,14 +157,14 @@ static int hpet_tick_resume(struct clock_event_device *evt)
157157
static int hpet_next_event(unsigned long delta,
158158
struct clock_event_device *evt)
159159
{
160-
unsigned int cnt;
161-
int res;
160+
u32 cnt;
161+
s32 res;
162162

163163
cnt = hpet_read(HPET_COUNTER);
164-
cnt += delta;
164+
cnt += (u32) delta;
165165
hpet_write(HPET_T0_CMP, cnt);
166166

167-
res = (int)(cnt - hpet_read(HPET_COUNTER));
167+
res = (s32)(cnt - hpet_read(HPET_COUNTER));
168168

169169
return res < HPET_MIN_CYCLES ? -ETIME : 0;
170170
}
@@ -230,7 +230,7 @@ void __init setup_hpet_timer(void)
230230

231231
cd = &per_cpu(hpet_clockevent_device, cpu);
232232
cd->name = "hpet";
233-
cd->rating = 320;
233+
cd->rating = 100;
234234
cd->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
235235
cd->set_state_shutdown = hpet_set_state_shutdown;
236236
cd->set_state_periodic = hpet_set_state_periodic;

‎arch/mips/mm/sc-rm7k.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -161,7 +161,7 @@ static void rm7k_tc_disable(void)
161161
local_irq_save(flags);
162162
blast_rm7k_tcache();
163163
clear_c0_config(RM7K_CONF_TE);
164-
local_irq_save(flags);
164+
local_irq_restore(flags);
165165
}
166166

167167
static void rm7k_sc_disable(void)

‎arch/mips/net/bpf_jit.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1199,7 +1199,7 @@ void bpf_jit_compile(struct bpf_prog *fp)
11991199

12001200
memset(&ctx, 0, sizeof(ctx));
12011201

1202-
ctx.offsets = kcalloc(fp->len, sizeof(*ctx.offsets), GFP_KERNEL);
1202+
ctx.offsets = kcalloc(fp->len + 1, sizeof(*ctx.offsets), GFP_KERNEL);
12031203
if (ctx.offsets == NULL)
12041204
return;
12051205

‎arch/x86/events/core.c

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -2319,7 +2319,7 @@ void
23192319
perf_callchain_user(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs)
23202320
{
23212321
struct stack_frame frame;
2322-
const void __user *fp;
2322+
const unsigned long __user *fp;
23232323

23242324
if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
23252325
/* TODO: We don't support guest os callchain now */
@@ -2332,7 +2332,7 @@ perf_callchain_user(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs
23322332
if (regs->flags & (X86_VM_MASK | PERF_EFLAGS_VM))
23332333
return;
23342334

2335-
fp = (void __user *)regs->bp;
2335+
fp = (unsigned long __user *)regs->bp;
23362336

23372337
perf_callchain_store(entry, regs->ip);
23382338

@@ -2345,16 +2345,17 @@ perf_callchain_user(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs
23452345
pagefault_disable();
23462346
while (entry->nr < entry->max_stack) {
23472347
unsigned long bytes;
2348+
23482349
frame.next_frame = NULL;
23492350
frame.return_address = 0;
23502351

2351-
if (!access_ok(VERIFY_READ, fp, 16))
2352+
if (!access_ok(VERIFY_READ, fp, sizeof(*fp) * 2))
23522353
break;
23532354

2354-
bytes = __copy_from_user_nmi(&frame.next_frame, fp, 8);
2355+
bytes = __copy_from_user_nmi(&frame.next_frame, fp, sizeof(*fp));
23552356
if (bytes != 0)
23562357
break;
2357-
bytes = __copy_from_user_nmi(&frame.return_address, fp+8, 8);
2358+
bytes = __copy_from_user_nmi(&frame.return_address, fp + 1, sizeof(*fp));
23582359
if (bytes != 0)
23592360
break;
23602361

‎arch/x86/events/intel/Makefile

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
obj-$(CONFIG_CPU_SUP_INTEL) += core.o bts.o cqm.o
22
obj-$(CONFIG_CPU_SUP_INTEL) += ds.o knc.o
33
obj-$(CONFIG_CPU_SUP_INTEL) += lbr.o p4.o p6.o pt.o
4-
obj-$(CONFIG_PERF_EVENTS_INTEL_RAPL) += intel-rapl.o
5-
intel-rapl-objs := rapl.o
4+
obj-$(CONFIG_PERF_EVENTS_INTEL_RAPL) += intel-rapl-perf.o
5+
intel-rapl-perf-objs := rapl.o
66
obj-$(CONFIG_PERF_EVENTS_INTEL_UNCORE) += intel-uncore.o
77
intel-uncore-objs := uncore.o uncore_nhmex.o uncore_snb.o uncore_snbep.o
88
obj-$(CONFIG_PERF_EVENTS_INTEL_CSTATE) += intel-cstate.o

0 commit comments

Comments
 (0)