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parakalinusw
paraka
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gpio: mt7621: Add a driver for MT7621
Add driver support for gpio of MT7621 SoC. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Reviewed-by: NeilBrown <neil@brown.name> [Switched wording WIDTH to STRIDE] Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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‎drivers/gpio/Kconfig

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@@ -359,6 +359,14 @@ config GPIO_MPC8XXX
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Say Y here if you're going to use hardware that connects to the
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MPC512x/831x/834x/837x/8572/8610/QorIQ GPIOs.
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config GPIO_MT7621
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bool "Mediatek MT7621 GPIO Support"
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depends on SOC_MT7620 || SOC_MT7621 || COMPILE_TEST
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select GPIO_GENERIC
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select GPIOLIB_IRQCHIP
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help
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Say yes here to support the Mediatek MT7621 SoC GPIO device
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config GPIO_MVEBU
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def_bool y
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depends on PLAT_ORION || ARCH_MVEBU

‎drivers/gpio/Makefile

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@@ -88,6 +88,7 @@ obj-$(CONFIG_GPIO_MOCKUP) += gpio-mockup.o
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obj-$(CONFIG_GPIO_MPC5200) += gpio-mpc5200.o
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obj-$(CONFIG_GPIO_MPC8XXX) += gpio-mpc8xxx.o
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obj-$(CONFIG_GPIO_MSIC) += gpio-msic.o
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obj-$(CONFIG_GPIO_MT7621) += gpio-mt7621.o
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obj-$(CONFIG_GPIO_MVEBU) += gpio-mvebu.o
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obj-$(CONFIG_GPIO_MXC) += gpio-mxc.o
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obj-$(CONFIG_GPIO_MXS) += gpio-mxs.o

‎drivers/gpio/gpio-mt7621.c

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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2013 John Crispin <blogic@openwrt.org>
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*/
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#include <linux/err.h>
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#include <linux/gpio/driver.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of_irq.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#define MTK_BANK_CNT 3
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#define MTK_BANK_WIDTH 32
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#define GPIO_BANK_STRIDE 0x04
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#define GPIO_REG_CTRL 0x00
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#define GPIO_REG_POL 0x10
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#define GPIO_REG_DATA 0x20
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#define GPIO_REG_DSET 0x30
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#define GPIO_REG_DCLR 0x40
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#define GPIO_REG_REDGE 0x50
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#define GPIO_REG_FEDGE 0x60
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#define GPIO_REG_HLVL 0x70
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#define GPIO_REG_LLVL 0x80
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#define GPIO_REG_STAT 0x90
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#define GPIO_REG_EDGE 0xA0
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struct mtk_gc {
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struct gpio_chip chip;
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spinlock_t lock;
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int bank;
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u32 rising;
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u32 falling;
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u32 hlevel;
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u32 llevel;
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};
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/**
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* struct mtk_data - state container for
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* data of the platform driver. It is 3
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* separate gpio-chip each one with its
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* own irq_chip.
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* @dev: device instance
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* @gpio_membase: memory base address
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* @gpio_irq: irq number from the device tree
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* @gc_map: array of the gpio chips
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*/
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struct mtk_data {
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struct device *dev;
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void __iomem *gpio_membase;
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int gpio_irq;
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struct mtk_gc gc_map[MTK_BANK_CNT];
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};
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static inline struct mtk_gc *
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to_mediatek_gpio(struct gpio_chip *chip)
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{
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return container_of(chip, struct mtk_gc, chip);
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}
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static inline void
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mtk_gpio_w32(struct mtk_gc *rg, u32 offset, u32 val)
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{
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struct gpio_chip *gc = &rg->chip;
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struct mtk_data *gpio_data = gpiochip_get_data(gc);
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offset = (rg->bank * GPIO_BANK_STRIDE) + offset;
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gc->write_reg(gpio_data->gpio_membase + offset, val);
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}
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static inline u32
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mtk_gpio_r32(struct mtk_gc *rg, u32 offset)
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{
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struct gpio_chip *gc = &rg->chip;
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struct mtk_data *gpio_data = gpiochip_get_data(gc);
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offset = (rg->bank * GPIO_BANK_STRIDE) + offset;
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return gc->read_reg(gpio_data->gpio_membase + offset);
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}
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static irqreturn_t
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mediatek_gpio_irq_handler(int irq, void *data)
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{
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struct gpio_chip *gc = data;
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struct mtk_gc *rg = to_mediatek_gpio(gc);
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irqreturn_t ret = IRQ_NONE;
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unsigned long pending;
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int bit;
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pending = mtk_gpio_r32(rg, GPIO_REG_STAT);
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for_each_set_bit(bit, &pending, MTK_BANK_WIDTH) {
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u32 map = irq_find_mapping(gc->irq.domain, bit);
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generic_handle_irq(map);
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mtk_gpio_w32(rg, GPIO_REG_STAT, BIT(bit));
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ret |= IRQ_HANDLED;
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}
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return ret;
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}
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static void
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mediatek_gpio_irq_unmask(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct mtk_gc *rg = to_mediatek_gpio(gc);
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int pin = d->hwirq;
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unsigned long flags;
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u32 rise, fall, high, low;
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spin_lock_irqsave(&rg->lock, flags);
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rise = mtk_gpio_r32(rg, GPIO_REG_REDGE);
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fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE);
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high = mtk_gpio_r32(rg, GPIO_REG_HLVL);
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low = mtk_gpio_r32(rg, GPIO_REG_LLVL);
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mtk_gpio_w32(rg, GPIO_REG_REDGE, rise | (BIT(pin) & rg->rising));
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mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall | (BIT(pin) & rg->falling));
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mtk_gpio_w32(rg, GPIO_REG_HLVL, high | (BIT(pin) & rg->hlevel));
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mtk_gpio_w32(rg, GPIO_REG_LLVL, low | (BIT(pin) & rg->llevel));
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spin_unlock_irqrestore(&rg->lock, flags);
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}
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static void
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mediatek_gpio_irq_mask(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct mtk_gc *rg = to_mediatek_gpio(gc);
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int pin = d->hwirq;
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unsigned long flags;
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u32 rise, fall, high, low;
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spin_lock_irqsave(&rg->lock, flags);
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rise = mtk_gpio_r32(rg, GPIO_REG_REDGE);
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fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE);
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high = mtk_gpio_r32(rg, GPIO_REG_HLVL);
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low = mtk_gpio_r32(rg, GPIO_REG_LLVL);
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mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall & ~BIT(pin));
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mtk_gpio_w32(rg, GPIO_REG_REDGE, rise & ~BIT(pin));
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mtk_gpio_w32(rg, GPIO_REG_HLVL, high & ~BIT(pin));
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mtk_gpio_w32(rg, GPIO_REG_LLVL, low & ~BIT(pin));
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spin_unlock_irqrestore(&rg->lock, flags);
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}
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static int
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mediatek_gpio_irq_type(struct irq_data *d, unsigned int type)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct mtk_gc *rg = to_mediatek_gpio(gc);
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int pin = d->hwirq;
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u32 mask = BIT(pin);
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if (type == IRQ_TYPE_PROBE) {
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if ((rg->rising | rg->falling |
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rg->hlevel | rg->llevel) & mask)
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return 0;
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type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
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}
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rg->rising &= ~mask;
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rg->falling &= ~mask;
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rg->hlevel &= ~mask;
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rg->llevel &= ~mask;
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switch (type & IRQ_TYPE_SENSE_MASK) {
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case IRQ_TYPE_EDGE_BOTH:
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rg->rising |= mask;
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rg->falling |= mask;
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break;
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case IRQ_TYPE_EDGE_RISING:
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rg->rising |= mask;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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rg->falling |= mask;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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rg->hlevel |= mask;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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rg->llevel |= mask;
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break;
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}
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return 0;
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}
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static struct irq_chip mediatek_gpio_irq_chip = {
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.irq_unmask = mediatek_gpio_irq_unmask,
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.irq_mask = mediatek_gpio_irq_mask,
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.irq_mask_ack = mediatek_gpio_irq_mask,
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.irq_set_type = mediatek_gpio_irq_type,
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};
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static int
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mediatek_gpio_xlate(struct gpio_chip *chip,
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const struct of_phandle_args *spec, u32 *flags)
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{
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int gpio = spec->args[0];
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struct mtk_gc *rg = to_mediatek_gpio(chip);
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if (rg->bank != gpio / MTK_BANK_WIDTH)
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return -EINVAL;
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if (flags)
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*flags = spec->args[1];
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return gpio % MTK_BANK_WIDTH;
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}
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static int
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mediatek_gpio_bank_probe(struct platform_device *pdev,
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struct device_node *node, int bank)
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{
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struct mtk_data *gpio = dev_get_drvdata(&pdev->dev);
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struct mtk_gc *rg;
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void __iomem *dat, *set, *ctrl, *diro;
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int ret;
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rg = &gpio->gc_map[bank];
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memset(rg, 0, sizeof(*rg));
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spin_lock_init(&rg->lock);
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rg->chip.of_node = node;
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rg->bank = bank;
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dat = gpio->gpio_membase + GPIO_REG_DATA +
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(rg->bank * GPIO_BANK_STRIDE);
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set = gpio->gpio_membase + GPIO_REG_DSET +
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(rg->bank * GPIO_BANK_STRIDE);
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ctrl = gpio->gpio_membase + GPIO_REG_DCLR +
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(rg->bank * GPIO_BANK_STRIDE);
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diro = gpio->gpio_membase + GPIO_REG_CTRL +
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(rg->bank * GPIO_BANK_STRIDE);
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ret = bgpio_init(&rg->chip, &pdev->dev, 4,
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dat, set, ctrl, diro, NULL, 0);
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if (ret) {
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dev_err(&pdev->dev, "bgpio_init() failed\n");
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return ret;
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}
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rg->chip.of_gpio_n_cells = 2;
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rg->chip.of_xlate = mediatek_gpio_xlate;
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rg->chip.label = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s-bank%d",
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dev_name(&pdev->dev), bank);
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ret = devm_gpiochip_add_data(&pdev->dev, &rg->chip, gpio);
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if (ret < 0) {
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dev_err(&pdev->dev, "Could not register gpio %d, ret=%d\n",
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rg->chip.ngpio, ret);
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return ret;
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}
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if (gpio->gpio_irq) {
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/*
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* Manually request the irq here instead of passing
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* a flow-handler to gpiochip_set_chained_irqchip,
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* because the irq is shared.
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*/
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ret = devm_request_irq(&pdev->dev, gpio->gpio_irq,
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mediatek_gpio_irq_handler, IRQF_SHARED,
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rg->chip.label, &rg->chip);
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if (ret) {
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dev_err(&pdev->dev, "Error requesting IRQ %d: %d\n",
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gpio->gpio_irq, ret);
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return ret;
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}
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ret = gpiochip_irqchip_add(&rg->chip, &mediatek_gpio_irq_chip,
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0, handle_simple_irq, IRQ_TYPE_NONE);
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if (ret) {
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dev_err(&pdev->dev, "failed to add gpiochip_irqchip\n");
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return ret;
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}
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gpiochip_set_chained_irqchip(&rg->chip, &mediatek_gpio_irq_chip,
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gpio->gpio_irq, NULL);
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}
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/* set polarity to low for all gpios */
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mtk_gpio_w32(rg, GPIO_REG_POL, 0);
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dev_info(&pdev->dev, "registering %d gpios\n", rg->chip.ngpio);
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return 0;
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}
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static int
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mediatek_gpio_probe(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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struct mtk_data *gpio_data;
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int i;
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gpio_data = devm_kzalloc(&pdev->dev, sizeof(*gpio_data), GFP_KERNEL);
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if (!gpio_data)
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return -ENOMEM;
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gpio_data->gpio_membase = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(gpio_data->gpio_membase))
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return PTR_ERR(gpio_data->gpio_membase);
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gpio_data->gpio_irq = irq_of_parse_and_map(np, 0);
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gpio_data->dev = &pdev->dev;
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platform_set_drvdata(pdev, gpio_data);
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mediatek_gpio_irq_chip.name = dev_name(&pdev->dev);
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for (i = 0; i < MTK_BANK_CNT; i++)
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mediatek_gpio_bank_probe(pdev, np, i);
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return 0;
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}
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static const struct of_device_id mediatek_gpio_match[] = {
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{ .compatible = "mediatek,mt7621-gpio" },
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{},
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};
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MODULE_DEVICE_TABLE(of, mediatek_gpio_match);
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static struct platform_driver mediatek_gpio_driver = {
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.probe = mediatek_gpio_probe,
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.driver = {
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.name = "mt7621_gpio",
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.of_match_table = mediatek_gpio_match,
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},
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};
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builtin_platform_driver(mediatek_gpio_driver);

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