@@ -75,7 +75,8 @@ enum BAR_ID {
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BAR_ID_1 /* Used for doorbells */
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};
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- static u32 qed_hw_bar_size (struct qed_hwfn * p_hwfn , enum BAR_ID bar_id )
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+ static u32 qed_hw_bar_size (struct qed_hwfn * p_hwfn ,
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+ struct qed_ptt * p_ptt , enum BAR_ID bar_id )
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{
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u32 bar_reg = (bar_id == BAR_ID_0 ?
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PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE );
@@ -84,7 +85,7 @@ static u32 qed_hw_bar_size(struct qed_hwfn *p_hwfn, enum BAR_ID bar_id)
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if (IS_VF (p_hwfn -> cdev ))
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return 1 << 17 ;
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- val = qed_rd (p_hwfn , p_hwfn -> p_main_ptt , bar_reg );
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+ val = qed_rd (p_hwfn , p_ptt , bar_reg );
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if (val )
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return 1 << (val + 15 );
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@@ -780,7 +781,7 @@ int qed_qm_reconf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
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qed_init_clear_rt_data (p_hwfn );
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/* prepare QM portion of runtime array */
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- qed_qm_init_pf (p_hwfn );
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+ qed_qm_init_pf (p_hwfn , p_ptt );
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/* activate init tool on runtime array */
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rc = qed_init_run (p_hwfn , p_ptt , PHASE_QM_PF , p_hwfn -> rel_pf_id ,
@@ -1191,6 +1192,57 @@ static void qed_init_cau_rt_data(struct qed_dev *cdev)
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}
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}
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+ static void qed_init_cache_line_size (struct qed_hwfn * p_hwfn ,
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+ struct qed_ptt * p_ptt )
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+ {
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+ u32 val , wr_mbs , cache_line_size ;
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+
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+ val = qed_rd (p_hwfn , p_ptt , PSWRQ2_REG_WR_MBS0 );
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+ switch (val ) {
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+ case 0 :
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+ wr_mbs = 128 ;
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+ break ;
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+ case 1 :
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+ wr_mbs = 256 ;
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+ break ;
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+ case 2 :
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+ wr_mbs = 512 ;
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+ break ;
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+ default :
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+ DP_INFO (p_hwfn ,
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+ "Unexpected value of PSWRQ2_REG_WR_MBS0 [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n" ,
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+ val );
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+ return ;
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+ }
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+
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+ cache_line_size = min_t (u32 , L1_CACHE_BYTES , wr_mbs );
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+ switch (cache_line_size ) {
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+ case 32 :
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+ val = 0 ;
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+ break ;
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+ case 64 :
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+ val = 1 ;
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+ break ;
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+ case 128 :
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+ val = 2 ;
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+ break ;
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+ case 256 :
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+ val = 3 ;
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+ break ;
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+ default :
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+ DP_INFO (p_hwfn ,
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+ "Unexpected value of cache line size [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n" ,
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+ cache_line_size );
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+ }
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+
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+ if (L1_CACHE_BYTES > wr_mbs )
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+ DP_INFO (p_hwfn ,
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+ "The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n" ,
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+ L1_CACHE_BYTES , wr_mbs );
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+
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+ STORE_RT_REG (p_hwfn , PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET , val );
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+ }
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+
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static int qed_hw_init_common (struct qed_hwfn * p_hwfn ,
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struct qed_ptt * p_ptt , int hw_mode )
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{
@@ -1227,17 +1279,7 @@ static int qed_hw_init_common(struct qed_hwfn *p_hwfn,
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qed_cxt_hw_init_common (p_hwfn );
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- /* Close gate from NIG to BRB/Storm; By default they are open, but
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- * we close them to prevent NIG from passing data to reset blocks.
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- * Should have been done in the ENGINE phase, but init-tool lacks
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- * proper port-pretend capabilities.
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- */
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- qed_wr (p_hwfn , p_ptt , NIG_REG_RX_BRB_OUT_EN , 0 );
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- qed_wr (p_hwfn , p_ptt , NIG_REG_STORM_OUT_EN , 0 );
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- qed_port_pretend (p_hwfn , p_ptt , p_hwfn -> port_id ^ 1 );
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- qed_wr (p_hwfn , p_ptt , NIG_REG_RX_BRB_OUT_EN , 0 );
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- qed_wr (p_hwfn , p_ptt , NIG_REG_STORM_OUT_EN , 0 );
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- qed_port_unpretend (p_hwfn , p_ptt );
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+ qed_init_cache_line_size (p_hwfn , p_ptt );
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rc = qed_init_run (p_hwfn , p_ptt , PHASE_ENGINE , ANY_PHASE_ID , hw_mode );
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if (rc )
@@ -1320,7 +1362,7 @@ qed_hw_init_pf_doorbell_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
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int rc = 0 ;
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u8 cond ;
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- db_bar_size = qed_hw_bar_size (p_hwfn , BAR_ID_1 );
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+ db_bar_size = qed_hw_bar_size (p_hwfn , p_ptt , BAR_ID_1 );
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if (p_hwfn -> cdev -> num_hwfns > 1 )
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db_bar_size /= 2 ;
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@@ -1431,7 +1473,7 @@ static int qed_hw_init_pf(struct qed_hwfn *p_hwfn,
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p_hwfn -> qm_info .pf_rl = 100000 ;
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}
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- qed_cxt_hw_init_pf (p_hwfn );
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+ qed_cxt_hw_init_pf (p_hwfn , p_ptt );
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qed_int_igu_init_rt (p_hwfn );
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@@ -1852,18 +1894,21 @@ int qed_hw_stop(struct qed_dev *cdev)
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return rc2 ;
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}
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- void qed_hw_stop_fastpath (struct qed_dev * cdev )
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+ int qed_hw_stop_fastpath (struct qed_dev * cdev )
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{
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int j ;
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for_each_hwfn (cdev , j ) {
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struct qed_hwfn * p_hwfn = & cdev -> hwfns [j ];
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- struct qed_ptt * p_ptt = p_hwfn -> p_main_ptt ;
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+ struct qed_ptt * p_ptt ;
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if (IS_VF (cdev )) {
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qed_vf_pf_int_cleanup (p_hwfn );
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continue ;
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}
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+ p_ptt = qed_ptt_acquire (p_hwfn );
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+ if (!p_ptt )
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+ return - EAGAIN ;
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DP_VERBOSE (p_hwfn ,
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NETIF_MSG_IFDOWN , "Shutting down the fastpath\n" );
@@ -1881,17 +1926,28 @@ void qed_hw_stop_fastpath(struct qed_dev *cdev)
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/* Need to wait 1ms to guarantee SBs are cleared */
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usleep_range (1000 , 2000 );
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+ qed_ptt_release (p_hwfn , p_ptt );
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}
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+
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+ return 0 ;
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}
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- void qed_hw_start_fastpath (struct qed_hwfn * p_hwfn )
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+ int qed_hw_start_fastpath (struct qed_hwfn * p_hwfn )
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{
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+ struct qed_ptt * p_ptt ;
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+
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if (IS_VF (p_hwfn -> cdev ))
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- return ;
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+ return 0 ;
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+
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+ p_ptt = qed_ptt_acquire (p_hwfn );
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+ if (!p_ptt )
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+ return - EAGAIN ;
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/* Re-open incoming traffic */
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- qed_wr (p_hwfn , p_hwfn -> p_main_ptt ,
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- NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF , 0x0 );
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+ qed_wr (p_hwfn , p_ptt , NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF , 0x0 );
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+ qed_ptt_release (p_hwfn , p_ptt );
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+
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+ return 0 ;
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}
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/* Free hwfn memory and resources acquired in hw_hwfn_prepare */
@@ -1989,12 +2045,17 @@ static void qed_hw_set_feat(struct qed_hwfn *p_hwfn)
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QED_VF_L2_QUE ));
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}
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+ if (p_hwfn -> hw_info .personality == QED_PCI_ISCSI )
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+ feat_num [QED_ISCSI_CQ ] = min_t (u32 , RESC_NUM (p_hwfn , QED_SB ),
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+ RESC_NUM (p_hwfn ,
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+ QED_CMDQS_CQS ));
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DP_VERBOSE (p_hwfn ,
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NETIF_MSG_PROBE ,
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- "#PF_L2_QUEUES=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d #SBS=%d\n" ,
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+ "#PF_L2_QUEUES=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d ISCSI_CQ=%d #SBS=%d\n" ,
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(int )FEAT_NUM (p_hwfn , QED_PF_L2_QUE ),
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(int )FEAT_NUM (p_hwfn , QED_VF_L2_QUE ),
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(int )FEAT_NUM (p_hwfn , QED_RDMA_CNQ ),
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+ (int )FEAT_NUM (p_hwfn , QED_ISCSI_CQ ),
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RESC_NUM (p_hwfn , QED_SB ));
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}
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@@ -2697,9 +2758,9 @@ qed_get_hw_info(struct qed_hwfn *p_hwfn,
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return qed_hw_get_resc (p_hwfn , p_ptt );
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}
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- static int qed_get_dev_info (struct qed_dev * cdev )
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+ static int qed_get_dev_info (struct qed_hwfn * p_hwfn , struct qed_ptt * p_ptt )
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{
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- struct qed_hwfn * p_hwfn = QED_LEADING_HWFN ( cdev ) ;
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+ struct qed_dev * cdev = p_hwfn -> cdev ;
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u16 device_id_mask ;
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u32 tmp ;
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@@ -2721,15 +2782,13 @@ static int qed_get_dev_info(struct qed_dev *cdev)
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return - EBUSY ;
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}
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- cdev -> chip_num = (u16 )qed_rd (p_hwfn , p_hwfn -> p_main_ptt ,
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- MISCS_REG_CHIP_NUM );
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- cdev -> chip_rev = (u16 )qed_rd (p_hwfn , p_hwfn -> p_main_ptt ,
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- MISCS_REG_CHIP_REV );
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+ cdev -> chip_num = (u16 )qed_rd (p_hwfn , p_ptt , MISCS_REG_CHIP_NUM );
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+ cdev -> chip_rev = (u16 )qed_rd (p_hwfn , p_ptt , MISCS_REG_CHIP_REV );
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+
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MASK_FIELD (CHIP_REV , cdev -> chip_rev );
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/* Learn number of HW-functions */
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- tmp = qed_rd (p_hwfn , p_hwfn -> p_main_ptt ,
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- MISCS_REG_CMT_ENABLED_FOR_PAIR );
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+ tmp = qed_rd (p_hwfn , p_ptt , MISCS_REG_CMT_ENABLED_FOR_PAIR );
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if (tmp & (1 << p_hwfn -> rel_pf_id )) {
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DP_NOTICE (cdev -> hwfns , "device in CMT mode\n" );
@@ -2738,11 +2797,10 @@ static int qed_get_dev_info(struct qed_dev *cdev)
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cdev -> num_hwfns = 1 ;
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}
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- cdev -> chip_bond_id = qed_rd (p_hwfn , p_hwfn -> p_main_ptt ,
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+ cdev -> chip_bond_id = qed_rd (p_hwfn , p_ptt ,
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MISCS_REG_CHIP_TEST_REG ) >> 4 ;
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MASK_FIELD (CHIP_BOND_ID , cdev -> chip_bond_id );
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- cdev -> chip_metal = (u16 )qed_rd (p_hwfn , p_hwfn -> p_main_ptt ,
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- MISCS_REG_CHIP_METAL );
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+ cdev -> chip_metal = (u16 )qed_rd (p_hwfn , p_ptt , MISCS_REG_CHIP_METAL );
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MASK_FIELD (CHIP_METAL , cdev -> chip_metal );
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DP_INFO (cdev -> hwfns ,
@@ -2795,7 +2853,7 @@ static int qed_hw_prepare_single(struct qed_hwfn *p_hwfn,
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/* First hwfn learns basic information, e.g., number of hwfns */
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if (!p_hwfn -> my_id ) {
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- rc = qed_get_dev_info (p_hwfn -> cdev );
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+ rc = qed_get_dev_info (p_hwfn , p_hwfn -> p_main_ptt );
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if (rc )
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goto err1 ;
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}
@@ -2866,11 +2924,14 @@ int qed_hw_prepare(struct qed_dev *cdev,
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u8 __iomem * addr ;
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/* adjust bar offset for second engine */
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- addr = cdev -> regview + qed_hw_bar_size (p_hwfn , BAR_ID_0 ) / 2 ;
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+ addr = cdev -> regview +
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+ qed_hw_bar_size (p_hwfn , p_hwfn -> p_main_ptt ,
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+ BAR_ID_0 ) / 2 ;
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p_regview = addr ;
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- /* adjust doorbell bar offset for second engine */
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- addr = cdev -> doorbells + qed_hw_bar_size (p_hwfn , BAR_ID_1 ) / 2 ;
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+ addr = cdev -> doorbells +
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+ qed_hw_bar_size (p_hwfn , p_hwfn -> p_main_ptt ,
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+ BAR_ID_1 ) / 2 ;
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p_doorbell = addr ;
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/* prepare second hw function */
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