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parisc: Add native high-resolution sched_clock() implementation
Add a native implementation for the sched_clock() function which utilizes the processor-internal cycle counter (Control Register 16) as high-resolution time source. With this patch we now get much more fine-grained resolutions in various in-kernel time measurements (e.g. when viewing the function tracing logs), and probably a more accurate scheduling on SMP systems. There are a few specific implementation details in this patch: 1. On a 32bit kernel we emulate the higher 32bits of the required 64-bit resolution of sched_clock() by increasing a per-cpu counter at every wrap-around of the 32bit cycle counter. 2. In a SMP system, the cycle counters of the various CPUs are not syncronized (similiar to the TSC in a x86_64 system). To cope with this we define HAVE_UNSTABLE_SCHED_CLOCK and let the upper layers do the adjustment work. 3. Since we need HAVE_UNSTABLE_SCHED_CLOCK, we need to provide a cmpxchg64() function even on a 32-bit kernel. 4. A 64-bit SMP kernel which is started on a UP system will mark the sched_clock() implementation as "stable", which means that we don't expect any jumps in the returned counter. This is true because we then run only on one CPU. Signed-off-by: Helge Deller <deller@gmx.de>
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‎arch/parisc/Kconfig

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -33,6 +33,7 @@ config PARISC
3333
select HAVE_ARCH_AUDITSYSCALL
3434
select HAVE_ARCH_SECCOMP_FILTER
3535
select HAVE_ARCH_TRACEHOOK
36+
select HAVE_UNSTABLE_SCHED_CLOCK if (SMP || !64BIT)
3637
select ARCH_NO_COHERENT_DMA_MMAP
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select CPU_NO_EFFICIENT_FFS
3839

‎arch/parisc/include/asm/cmpxchg.h

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -52,16 +52,15 @@ extern void __cmpxchg_called_with_bad_pointer(void);
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/* __cmpxchg_u32/u64 defined in arch/parisc/lib/bitops.c */
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extern unsigned long __cmpxchg_u32(volatile unsigned int *m, unsigned int old,
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unsigned int new_);
55-
extern unsigned long __cmpxchg_u64(volatile unsigned long *ptr,
56-
unsigned long old, unsigned long new_);
55+
extern u64 __cmpxchg_u64(volatile u64 *ptr, u64 old, u64 new_);
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5857
/* don't worry...optimizer will get rid of most of this */
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static inline unsigned long
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__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new_, int size)
6160
{
6261
switch (size) {
6362
#ifdef CONFIG_64BIT
64-
case 8: return __cmpxchg_u64((unsigned long *)ptr, old, new_);
63+
case 8: return __cmpxchg_u64((u64 *)ptr, old, new_);
6564
#endif
6665
case 4: return __cmpxchg_u32((unsigned int *)ptr,
6766
(unsigned int)old, (unsigned int)new_);
@@ -86,7 +85,7 @@ static inline unsigned long __cmpxchg_local(volatile void *ptr,
8685
{
8786
switch (size) {
8887
#ifdef CONFIG_64BIT
89-
case 8: return __cmpxchg_u64((unsigned long *)ptr, old, new_);
88+
case 8: return __cmpxchg_u64((u64 *)ptr, old, new_);
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#endif
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case 4: return __cmpxchg_u32(ptr, old, new_);
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default:
@@ -111,4 +110,6 @@ static inline unsigned long __cmpxchg_local(volatile void *ptr,
111110
#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
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#endif
113112

113+
#define cmpxchg64(ptr, o, n) __cmpxchg_u64(ptr, o, n)
114+
114115
#endif /* _ASM_PARISC_CMPXCHG_H_ */

‎arch/parisc/kernel/time.c

Lines changed: 62 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -38,6 +38,18 @@
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3939
static unsigned long clocktick __read_mostly; /* timer cycles per tick */
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41+
#ifndef CONFIG_64BIT
42+
/*
43+
* The processor-internal cycle counter (Control Register 16) is used as time
44+
* source for the sched_clock() function. This register is 64bit wide on a
45+
* 64-bit kernel and 32bit on a 32-bit kernel. Since sched_clock() always
46+
* requires a 64bit counter we emulate on the 32-bit kernel the higher 32bits
47+
* with a per-cpu variable which we increase every time the counter
48+
* wraps-around (which happens every ~4 secounds).
49+
*/
50+
static DEFINE_PER_CPU(unsigned long, cr16_high_32_bits);
51+
#endif
52+
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/*
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* We keep time on PA-RISC Linux by using the Interval Timer which is
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* a pair of registers; one is read-only and one is write-only; both
@@ -108,6 +120,12 @@ irqreturn_t __irq_entry timer_interrupt(int irq, void *dev_id)
108120
*/
109121
mtctl(next_tick, 16);
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123+
#if !defined(CONFIG_64BIT)
124+
/* check for overflow on a 32bit kernel (every ~4 seconds). */
125+
if (unlikely(next_tick < now))
126+
this_cpu_inc(cr16_high_32_bits);
127+
#endif
128+
111129
/* Skip one clocktick on purpose if we missed next_tick.
112130
* The new CR16 must be "later" than current CR16 otherwise
113131
* itimer would not fire until CR16 wrapped - e.g 4 seconds
@@ -219,6 +237,12 @@ void __init start_cpu_itimer(void)
219237
unsigned int cpu = smp_processor_id();
220238
unsigned long next_tick = mfctl(16) + clocktick;
221239

240+
#if defined(CONFIG_HAVE_UNSTABLE_SCHED_CLOCK) && defined(CONFIG_64BIT)
241+
/* With multiple 64bit CPUs online, the cr16's are not syncronized. */
242+
if (cpu != 0)
243+
clear_sched_clock_stable();
244+
#endif
245+
222246
mtctl(next_tick, 16); /* kick off Interval Timer (CR16) */
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224248
per_cpu(cpu_data, cpu).it_value = next_tick;
@@ -246,15 +270,52 @@ void read_persistent_clock(struct timespec *ts)
246270
}
247271
}
248272

273+
274+
/*
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* sched_clock() framework
276+
*/
277+
278+
static u32 cyc2ns_mul __read_mostly;
279+
static u32 cyc2ns_shift __read_mostly;
280+
281+
u64 sched_clock(void)
282+
{
283+
u64 now;
284+
285+
/* Get current cycle counter (Control Register 16). */
286+
#ifdef CONFIG_64BIT
287+
now = mfctl(16);
288+
#else
289+
now = mfctl(16) + (((u64) this_cpu_read(cr16_high_32_bits)) << 32);
290+
#endif
291+
292+
/* return the value in ns (cycles_2_ns) */
293+
return mul_u64_u32_shr(now, cyc2ns_mul, cyc2ns_shift);
294+
}
295+
296+
297+
/*
298+
* timer interrupt and sched_clock() initialization
299+
*/
300+
249301
void __init time_init(void)
250302
{
251303
unsigned long current_cr16_khz;
252304

305+
current_cr16_khz = PAGE0->mem_10msec/10; /* kHz */
253306
clocktick = (100 * PAGE0->mem_10msec) / HZ;
254307

308+
/* calculate mult/shift values for cr16 */
309+
clocks_calc_mult_shift(&cyc2ns_mul, &cyc2ns_shift, current_cr16_khz,
310+
NSEC_PER_MSEC, 0);
311+
312+
#if defined(CONFIG_HAVE_UNSTABLE_SCHED_CLOCK) && defined(CONFIG_64BIT)
313+
/* At bootup only one 64bit CPU is online and cr16 is "stable" */
314+
set_sched_clock_stable();
315+
#endif
316+
255317
start_cpu_itimer(); /* get CPU 0 started */
256318

257319
/* register at clocksource framework */
258-
current_cr16_khz = PAGE0->mem_10msec/10; /* kHz */
259320
clocksource_register_khz(&clocksource_cr16, current_cr16_khz);
260321
}

‎arch/parisc/lib/bitops.c

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -55,19 +55,17 @@ unsigned long __xchg8(char x, char *ptr)
5555
}
5656

5757

58-
#ifdef CONFIG_64BIT
59-
unsigned long __cmpxchg_u64(volatile unsigned long *ptr, unsigned long old, unsigned long new)
58+
u64 __cmpxchg_u64(volatile u64 *ptr, u64 old, u64 new)
6059
{
6160
unsigned long flags;
62-
unsigned long prev;
61+
u64 prev;
6362

6463
_atomic_spin_lock_irqsave(ptr, flags);
6564
if ((prev = *ptr) == old)
6665
*ptr = new;
6766
_atomic_spin_unlock_irqrestore(ptr, flags);
6867
return prev;
6968
}
70-
#endif
7169

7270
unsigned long __cmpxchg_u32(volatile unsigned int *ptr, unsigned int old, unsigned int new)
7371
{

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