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Merge tag 'timers-core-2022-10-05' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull timer updates from Thomas Gleixner: "A boring time, timekeeping, timers update: - No core code changes - No new clocksource/event driver - Cleanup of the TI DM clocksource/event driver - The usual set of device tree binding updates - Small improvement, fixes and cleanups all over the place" * tag 'timers-core-2022-10-05' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (22 commits) clocksource/drivers/arm_arch_timer: Fix CNTPCT_LO and CNTVCT_LO value clocksource/drivers/imx-sysctr: handle nxp,no-divider property dt-bindings: timer: nxp,sysctr-timer: add nxp,no-divider property clocksource/drivers/timer-ti-dm: Get clock in probe with devm_clk_get() clocksource/drivers/timer-ti-dm: Add flag to detect omap1 clocksource/drivers/timer-ti-dm: Move struct omap_dm_timer fields to driver clocksource/drivers/timer-ti-dm: Use runtime PM directly and check errors clocksource/drivers/timer-ti-dm: Move private defines to the driver clocksource/drivers/timer-ti-dm: Simplify register access further clocksource/drivers/timer-ti-dm: Simplify register writes with dmtimer_write() clocksource/drivers/timer-ti-dm: Simplify register reads with dmtimer_read() clocksource/drivers/timer-ti-dm: Drop unused functions clocksource/drivers/timer-gxp: Add missing error handling in gxp_timer_probe clocksource/drivers/arm_arch_timer: Fix handling of ARM erratum 858921 clocksource/drivers/exynos_mct: Enable building on ARTPEC clocksource/drivers/exynos_mct: Support local-timers property clocksource/drivers/exynos_mct: Support frc-shared property dt-bindings: timer: exynos4210-mct: Add ARTPEC-8 MCT support clocksource/drivers/sun4i: Add definition of clear interrupt clocksource/drivers/renesas-ostm: Add support for RZ/V2L SoC ...
2 parents 7f6dcff + 6cb5ce1 commit 55be608

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13 files changed

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‎Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -25,6 +25,7 @@ Required properties:
2525
For those SoCs that use SYST
2626
* "mediatek,mt8183-timer" for MT8183 compatible timers (SYST)
2727
* "mediatek,mt8186-timer" for MT8186 compatible timers (SYST)
28+
* "mediatek,mt8188-timer" for MT8188 compatible timers (SYST)
2829
* "mediatek,mt8192-timer" for MT8192 compatible timers (SYST)
2930
* "mediatek,mt8195-timer" for MT8195 compatible timers (SYST)
3031
* "mediatek,mt7629-timer" for MT7629 compatible timers (SYST)

‎Documentation/devicetree/bindings/timer/nxp,sysctr-timer.yaml

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -32,6 +32,10 @@ properties:
3232
clock-names:
3333
const: per
3434

35+
nxp,no-divider:
36+
description: if present, means there is no internal base clk divider.
37+
type: boolean
38+
3539
required:
3640
- compatible
3741
- reg

‎Documentation/devicetree/bindings/timer/renesas,tmu.yaml

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -37,6 +37,7 @@ properties:
3737
- renesas,tmu-r8a77990 # R-Car E3
3838
- renesas,tmu-r8a77995 # R-Car D3
3939
- renesas,tmu-r8a779a0 # R-Car V3U
40+
- renesas,tmu-r8a779f0 # R-Car S4-8
4041
- const: renesas,tmu
4142

4243
reg:

‎Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml

Lines changed: 26 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -25,6 +25,7 @@ properties:
2525
- samsung,exynos4412-mct
2626
- items:
2727
- enum:
28+
- axis,artpec8-mct
2829
- samsung,exynos3250-mct
2930
- samsung,exynos5250-mct
3031
- samsung,exynos5260-mct
@@ -45,6 +46,19 @@ properties:
4546
reg:
4647
maxItems: 1
4748

49+
samsung,frc-shared:
50+
type: boolean
51+
description: |
52+
Indicates that the hardware requires that this processor share the
53+
free-running counter with a different (main) processor.
54+
55+
samsung,local-timers:
56+
$ref: /schemas/types.yaml#/definitions/uint32-array
57+
minItems: 1
58+
maxItems: 16
59+
description: |
60+
List of indices of local timers usable from this processor.
61+
4862
interrupts:
4963
description: |
5064
Interrupts should be put in specific order. This is, the local timer
@@ -74,6 +88,17 @@ required:
7488
- reg
7589

7690
allOf:
91+
- if:
92+
not:
93+
properties:
94+
compatible:
95+
contains:
96+
enum:
97+
- axis,artpec8-mct
98+
then:
99+
properties:
100+
samsung,local-timers: false
101+
samsung,frc-shared: false
77102
- if:
78103
properties:
79104
compatible:
@@ -101,6 +126,7 @@ allOf:
101126
compatible:
102127
contains:
103128
enum:
129+
- axis,artpec8-mct
104130
- samsung,exynos5260-mct
105131
- samsung,exynos5420-mct
106132
- samsung,exynos5433-mct

‎drivers/clocksource/Kconfig

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -434,7 +434,7 @@ config ATMEL_TCB_CLKSRC
434434
config CLKSRC_EXYNOS_MCT
435435
bool "Exynos multi core timer driver" if COMPILE_TEST
436436
depends on ARM || ARM64
437-
depends on ARCH_EXYNOS || COMPILE_TEST
437+
depends on ARCH_ARTPEC || ARCH_EXYNOS || COMPILE_TEST
438438
help
439439
Support for Multi Core Timer controller on Exynos SoCs.
440440

‎drivers/clocksource/arm_arch_timer.c

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -44,8 +44,8 @@
4444
#define CNTACR_RWVT BIT(4)
4545
#define CNTACR_RWPT BIT(5)
4646

47-
#define CNTVCT_LO 0x00
48-
#define CNTPCT_LO 0x08
47+
#define CNTPCT_LO 0x00
48+
#define CNTVCT_LO 0x08
4949
#define CNTFRQ 0x10
5050
#define CNTP_CVAL_LO 0x20
5151
#define CNTP_CTL 0x2c
@@ -473,6 +473,8 @@ static const struct arch_timer_erratum_workaround ool_workarounds[] = {
473473
.desc = "ARM erratum 858921",
474474
.read_cntpct_el0 = arm64_858921_read_cntpct_el0,
475475
.read_cntvct_el0 = arm64_858921_read_cntvct_el0,
476+
.set_next_event_phys = erratum_set_next_event_phys,
477+
.set_next_event_virt = erratum_set_next_event_virt,
476478
},
477479
#endif
478480
#ifdef CONFIG_SUN50I_ERRATUM_UNKNOWN1

‎drivers/clocksource/exynos_mct.c

Lines changed: 74 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -33,7 +33,7 @@
3333
#define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248)
3434
#define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C)
3535
#define _EXYNOS4_MCT_L_BASE EXYNOS4_MCTREG(0x300)
36-
#define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * x))
36+
#define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * (x)))
3737
#define EXYNOS4_MCT_L_MASK (0xffffff00)
3838

3939
#define MCT_L_TCNTB_OFFSET (0x00)
@@ -66,6 +66,8 @@
6666
#define MCT_L0_IRQ 4
6767
/* Max number of IRQ as per DT binding document */
6868
#define MCT_NR_IRQS 20
69+
/* Max number of local timers */
70+
#define MCT_NR_LOCAL (MCT_NR_IRQS - MCT_L0_IRQ)
6971

7072
enum {
7173
MCT_INT_SPI,
@@ -233,9 +235,16 @@ static cycles_t exynos4_read_current_timer(void)
233235
}
234236
#endif
235237

236-
static int __init exynos4_clocksource_init(void)
238+
static int __init exynos4_clocksource_init(bool frc_shared)
237239
{
238-
exynos4_mct_frc_start();
240+
/*
241+
* When the frc is shared, the main processer should have already
242+
* turned it on and we shouldn't be writing to TCON.
243+
*/
244+
if (frc_shared)
245+
mct_frc.resume = NULL;
246+
else
247+
exynos4_mct_frc_start();
239248

240249
#if defined(CONFIG_ARM)
241250
exynos4_delay_timer.read_current_timer = &exynos4_read_current_timer;
@@ -449,7 +458,6 @@ static int exynos4_mct_starting_cpu(unsigned int cpu)
449458
per_cpu_ptr(&percpu_mct_tick, cpu);
450459
struct clock_event_device *evt = &mevt->evt;
451460

452-
mevt->base = EXYNOS4_MCT_L_BASE(cpu);
453461
snprintf(mevt->name, sizeof(mevt->name), "mct_tick%d", cpu);
454462

455463
evt->name = mevt->name;
@@ -520,8 +528,17 @@ static int __init exynos4_timer_resources(struct device_node *np)
520528
return 0;
521529
}
522530

531+
/**
532+
* exynos4_timer_interrupts - initialize MCT interrupts
533+
* @np: device node for MCT
534+
* @int_type: interrupt type, MCT_INT_PPI or MCT_INT_SPI
535+
* @local_idx: array mapping CPU numbers to local timer indices
536+
* @nr_local: size of @local_idx array
537+
*/
523538
static int __init exynos4_timer_interrupts(struct device_node *np,
524-
unsigned int int_type)
539+
unsigned int int_type,
540+
const u32 *local_idx,
541+
size_t nr_local)
525542
{
526543
int nr_irqs, i, err, cpu;
527544

@@ -554,13 +571,21 @@ static int __init exynos4_timer_interrupts(struct device_node *np,
554571
} else {
555572
for_each_possible_cpu(cpu) {
556573
int mct_irq;
574+
unsigned int irq_idx;
557575
struct mct_clock_event_device *pcpu_mevt =
558576
per_cpu_ptr(&percpu_mct_tick, cpu);
559577

578+
if (cpu >= nr_local) {
579+
err = -EINVAL;
580+
goto out_irq;
581+
}
582+
583+
irq_idx = MCT_L0_IRQ + local_idx[cpu];
584+
560585
pcpu_mevt->evt.irq = -1;
561-
if (MCT_L0_IRQ + cpu >= ARRAY_SIZE(mct_irqs))
586+
if (irq_idx >= ARRAY_SIZE(mct_irqs))
562587
break;
563-
mct_irq = mct_irqs[MCT_L0_IRQ + cpu];
588+
mct_irq = mct_irqs[irq_idx];
564589

565590
irq_set_status_flags(mct_irq, IRQ_NOAUTOEN);
566591
if (request_irq(mct_irq,
@@ -576,6 +601,17 @@ static int __init exynos4_timer_interrupts(struct device_node *np,
576601
}
577602
}
578603

604+
for_each_possible_cpu(cpu) {
605+
struct mct_clock_event_device *mevt = per_cpu_ptr(&percpu_mct_tick, cpu);
606+
607+
if (cpu >= nr_local) {
608+
err = -EINVAL;
609+
goto out_irq;
610+
}
611+
612+
mevt->base = EXYNOS4_MCT_L_BASE(local_idx[cpu]);
613+
}
614+
579615
/* Install hotplug callbacks which configure the timer on this CPU */
580616
err = cpuhp_setup_state(CPUHP_AP_EXYNOS4_MCT_TIMER_STARTING,
581617
"clockevents/exynos4/mct_timer:starting",
@@ -605,20 +641,49 @@ static int __init exynos4_timer_interrupts(struct device_node *np,
605641

606642
static int __init mct_init_dt(struct device_node *np, unsigned int int_type)
607643
{
644+
bool frc_shared = of_property_read_bool(np, "samsung,frc-shared");
645+
u32 local_idx[MCT_NR_LOCAL] = {0};
646+
int nr_local;
608647
int ret;
609648

649+
nr_local = of_property_count_u32_elems(np, "samsung,local-timers");
650+
if (nr_local == 0)
651+
return -EINVAL;
652+
if (nr_local > 0) {
653+
if (nr_local > ARRAY_SIZE(local_idx))
654+
return -EINVAL;
655+
656+
ret = of_property_read_u32_array(np, "samsung,local-timers",
657+
local_idx, nr_local);
658+
if (ret)
659+
return ret;
660+
} else {
661+
int i;
662+
663+
nr_local = ARRAY_SIZE(local_idx);
664+
for (i = 0; i < nr_local; i++)
665+
local_idx[i] = i;
666+
}
667+
610668
ret = exynos4_timer_resources(np);
611669
if (ret)
612670
return ret;
613671

614-
ret = exynos4_timer_interrupts(np, int_type);
672+
ret = exynos4_timer_interrupts(np, int_type, local_idx, nr_local);
615673
if (ret)
616674
return ret;
617675

618-
ret = exynos4_clocksource_init();
676+
ret = exynos4_clocksource_init(frc_shared);
619677
if (ret)
620678
return ret;
621679

680+
/*
681+
* When the FRC is shared with a main processor, this secondary
682+
* processor cannot use the global comparator.
683+
*/
684+
if (frc_shared)
685+
return ret;
686+
622687
return exynos4_clockevent_init();
623688
}
624689

‎drivers/clocksource/renesas-ostm.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -224,7 +224,7 @@ static int __init ostm_init(struct device_node *np)
224224

225225
TIMER_OF_DECLARE(ostm, "renesas,ostm", ostm_init);
226226

227-
#ifdef CONFIG_ARCH_R9A07G044
227+
#ifdef CONFIG_ARCH_RZG2L
228228
static int __init ostm_probe(struct platform_device *pdev)
229229
{
230230
struct device *dev = &pdev->dev;

‎drivers/clocksource/timer-gxp.c

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -171,6 +171,7 @@ static int gxp_timer_probe(struct platform_device *pdev)
171171
{
172172
struct platform_device *gxp_watchdog_device;
173173
struct device *dev = &pdev->dev;
174+
int ret;
174175

175176
if (!gxp_timer) {
176177
pr_err("Gxp Timer not initialized, cannot create watchdog");
@@ -187,7 +188,11 @@ static int gxp_timer_probe(struct platform_device *pdev)
187188
gxp_watchdog_device->dev.platform_data = gxp_timer->counter;
188189
gxp_watchdog_device->dev.parent = dev;
189190

190-
return platform_device_add(gxp_watchdog_device);
191+
ret = platform_device_add(gxp_watchdog_device);
192+
if (ret)
193+
platform_device_put(gxp_watchdog_device);
194+
195+
return ret;
191196
}
192197

193198
static const struct of_device_id gxp_timer_of_match[] = {

‎drivers/clocksource/timer-imx-sysctr.c

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -134,8 +134,10 @@ static int __init sysctr_timer_init(struct device_node *np)
134134
if (ret)
135135
return ret;
136136

137-
/* system counter clock is divided by 3 internally */
138-
to_sysctr.of_clk.rate /= SYS_CTR_CLK_DIV;
137+
if (!of_property_read_bool(np, "nxp,no-divider")) {
138+
/* system counter clock is divided by 3 internally */
139+
to_sysctr.of_clk.rate /= SYS_CTR_CLK_DIV;
140+
}
139141

140142
sys_ctr_base = timer_of_base(&to_sysctr);
141143
cmpcr = readl(sys_ctr_base + CMPCR);

‎drivers/clocksource/timer-sun4i.c

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -26,6 +26,7 @@
2626
#define TIMER_IRQ_EN_REG 0x00
2727
#define TIMER_IRQ_EN(val) BIT(val)
2828
#define TIMER_IRQ_ST_REG 0x04
29+
#define TIMER_IRQ_CLEAR(val) BIT(val)
2930
#define TIMER_CTL_REG(val) (0x10 * val + 0x10)
3031
#define TIMER_CTL_ENABLE BIT(0)
3132
#define TIMER_CTL_RELOAD BIT(1)
@@ -123,7 +124,7 @@ static int sun4i_clkevt_next_event(unsigned long evt,
123124

124125
static void sun4i_timer_clear_interrupt(void __iomem *base)
125126
{
126-
writel(TIMER_IRQ_EN(0), base + TIMER_IRQ_ST_REG);
127+
writel(TIMER_IRQ_CLEAR(0), base + TIMER_IRQ_ST_REG);
127128
}
128129

129130
static irqreturn_t sun4i_timer_interrupt(int irq, void *dev_id)

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