drm/radeon: program DCE2 audio dto just like DCE3

alexdeucher · alexdeucher · commit 55d4e020fb8d · 2013-12-02T16:40:42.000-05:00
Seems to work like the DCE3 version despite what the register spec says. bug: https://bugs.freedesktop.org/show_bug.cgi?id=71975 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/r600_hdmi.c
@@ -304,9 +304,9 @@ void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock)
 			WREG32(DCCG_AUDIO_DTO1_MODULE, dto_modulo);
 			WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */
 		}
-	} else if (ASIC_IS_DCE3(rdev)) {
+	} else {
 		/* according to the reg specs, this should DCE3.2 only, but in
-		 * practice it seems to cover DCE3.0/3.1 as well.
+		 * practice it seems to cover DCE2.0/3.0/3.1 as well.
 		 */
 		if (dig->dig_encoder == 0) {
 			WREG32(DCCG_AUDIO_DTO0_PHASE, base_rate * 100);
@@ -317,10 +317,6 @@ void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock)
 			WREG32(DCCG_AUDIO_DTO1_MODULE, clock * 100);
 			WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */
 		}
-	} else {
-		/* according to the reg specs, this should be DCE2.0 and DCE3.0/3.1 */
-		WREG32(AUDIO_DTO, AUDIO_DTO_PHASE(base_rate / 10) |
-		       AUDIO_DTO_MODULE(clock / 10));
 	}
 }
 

Original file line number	Diff line number	Diff line change
`@@ -304,9 +304,9 @@ void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock)`
`304`	`304`	`WREG32(DCCG_AUDIO_DTO1_MODULE, dto_modulo);`
`305`	`305`	`WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */`
`306`	`306`	`}`
`307`		`- } else if (ASIC_IS_DCE3(rdev)) {`
	`307`	`+ } else {`
`308`	`308`	`/* according to the reg specs, this should DCE3.2 only, but in`
`309`		`- * practice it seems to cover DCE3.0/3.1 as well.`
	`309`	`+ * practice it seems to cover DCE2.0/3.0/3.1 as well.`
`310`	`310`	`*/`
`311`	`311`	`if (dig->dig_encoder == 0) {`
`312`	`312`	`WREG32(DCCG_AUDIO_DTO0_PHASE, base_rate * 100);`
`@@ -317,10 +317,6 @@ void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock)`
`317`	`317`	`WREG32(DCCG_AUDIO_DTO1_MODULE, clock * 100);`
`318`	`318`	`WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */`
`319`	`319`	`}`
`320`		`- } else {`
`321`		`- /* according to the reg specs, this should be DCE2.0 and DCE3.0/3.1 */`
`322`		`- WREG32(AUDIO_DTO, AUDIO_DTO_PHASE(base_rate / 10) \|`
`323`		`- AUDIO_DTO_MODULE(clock / 10));`
`324`	`320`	`}`
`325`	`321`	`}`
`326`	`322`