RISC-V: Don't set cacheinfo.{physical_line_partition,attributes}

palmer-dabbelt · palmer-dabbelt · commit 566d6c428ead · 2018-10-22T17:03:35.000-07:00
These are just hard coded in the RISC-V port, which doesn't make any
sense.  We should probably be setting these from device tree entries
when they exist, but for now I think it's saner to just leave them all
as their default values.

Signed-off-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
Reviewed-by: Christoph Hellwig &lt;hch@lst.de&gt;
Reviewed-by: Jeremy Linton &lt;jeremy.linton@arm.com&gt;
Signed-off-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c
@@ -22,13 +22,6 @@ static void ci_leaf_init(struct cacheinfo *this_leaf,
 {
 	this_leaf->level = level;
 	this_leaf->type = type;
-	/* not a sector cache */
-	this_leaf->physical_line_partition = 1;
-	/* TODO: Add to DTS */
-	this_leaf->attributes =
-		CACHE_WRITE_BACK
-		| CACHE_READ_ALLOCATE
-		| CACHE_WRITE_ALLOCATE;
 }
 
 static int __init_cache_level(unsigned int cpu)

Original file line number	Diff line number	Diff line change
`@@ -22,13 +22,6 @@ static void ci_leaf_init(struct cacheinfo *this_leaf,`
`22`	`22`	`{`
`23`	`23`	`this_leaf->level = level;`
`24`	`24`	`this_leaf->type = type;`
`25`		`- /* not a sector cache */`
`26`		`- this_leaf->physical_line_partition = 1;`
`27`		`- /* TODO: Add to DTS */`
`28`		`- this_leaf->attributes =`
`29`		`- CACHE_WRITE_BACK`
`30`		`- \| CACHE_READ_ALLOCATE`
`31`		`- \| CACHE_WRITE_ALLOCATE;`
`32`	`25`	`}`
`33`	`26`
`34`	`27`	`static int __init_cache_level(unsigned int cpu)`