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37 | 37 | #define SUN4I_TCON_GINT1_REG 0x8
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38 | 38 |
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39 | 39 | #define SUN4I_TCON_FRM_CTL_REG 0x10
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40 |
| -#define SUN4I_TCON_FRM_CTL_EN BIT(31) |
41 |
| - |
42 |
| -#define SUN4I_TCON_FRM_SEED_PR_REG 0x14 |
43 |
| -#define SUN4I_TCON_FRM_SEED_PG_REG 0x18 |
44 |
| -#define SUN4I_TCON_FRM_SEED_PB_REG 0x1c |
45 |
| -#define SUN4I_TCON_FRM_SEED_LR_REG 0x20 |
46 |
| -#define SUN4I_TCON_FRM_SEED_LG_REG 0x24 |
47 |
| -#define SUN4I_TCON_FRM_SEED_LB_REG 0x28 |
48 |
| -#define SUN4I_TCON_FRM_TBL0_REG 0x2c |
49 |
| -#define SUN4I_TCON_FRM_TBL1_REG 0x30 |
50 |
| -#define SUN4I_TCON_FRM_TBL2_REG 0x34 |
51 |
| -#define SUN4I_TCON_FRM_TBL3_REG 0x38 |
| 40 | +#define SUN4I_TCON0_FRM_CTL_EN BIT(31) |
| 41 | +#define SUN4I_TCON0_FRM_CTL_MODE_R BIT(6) |
| 42 | +#define SUN4I_TCON0_FRM_CTL_MODE_G BIT(5) |
| 43 | +#define SUN4I_TCON0_FRM_CTL_MODE_B BIT(4) |
| 44 | + |
| 45 | +#define SUN4I_TCON0_FRM_SEED_PR_REG 0x14 |
| 46 | +#define SUN4I_TCON0_FRM_SEED_PG_REG 0x18 |
| 47 | +#define SUN4I_TCON0_FRM_SEED_PB_REG 0x1c |
| 48 | +#define SUN4I_TCON0_FRM_SEED_LR_REG 0x20 |
| 49 | +#define SUN4I_TCON0_FRM_SEED_LG_REG 0x24 |
| 50 | +#define SUN4I_TCON0_FRM_SEED_LB_REG 0x28 |
| 51 | +#define SUN4I_TCON0_FRM_TBL0_REG 0x2c |
| 52 | +#define SUN4I_TCON0_FRM_TBL1_REG 0x30 |
| 53 | +#define SUN4I_TCON0_FRM_TBL2_REG 0x34 |
| 54 | +#define SUN4I_TCON0_FRM_TBL3_REG 0x38 |
52 | 55 |
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53 | 56 | #define SUN4I_TCON0_CTL_REG 0x40
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54 | 57 | #define SUN4I_TCON0_CTL_TCON_ENABLE BIT(31)
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