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neuschaeferlinusw
neuschaefer
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gpio: hlwd: Add basic IRQ support
This patch implements level-triggered IRQs in the Hollywood GPIO driver. Edge triggered interrupts are not supported in this GPIO controller, so I moved their emulation into a separate patch. Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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‎drivers/gpio/Kconfig

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -258,6 +258,7 @@ config GPIO_HLWD
258258
tristate "Nintendo Wii (Hollywood) GPIO"
259259
depends on OF_GPIO
260260
select GPIO_GENERIC
261+
select GPIOLIB_IRQCHIP
261262
help
262263
Select this to support the GPIO controller of the Nintendo Wii.
263264

‎drivers/gpio/gpio-hlwd.c

Lines changed: 135 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -48,9 +48,107 @@
4848

4949
struct hlwd_gpio {
5050
struct gpio_chip gpioc;
51+
struct irq_chip irqc;
5152
void __iomem *regs;
53+
int irq;
5254
};
5355

56+
static void hlwd_gpio_irqhandler(struct irq_desc *desc)
57+
{
58+
struct hlwd_gpio *hlwd =
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gpiochip_get_data(irq_desc_get_handler_data(desc));
60+
struct irq_chip *chip = irq_desc_get_chip(desc);
61+
unsigned long flags;
62+
unsigned long pending;
63+
int hwirq;
64+
65+
spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);
66+
pending = ioread32be(hlwd->regs + HW_GPIOB_INTFLAG);
67+
pending &= ioread32be(hlwd->regs + HW_GPIOB_INTMASK);
68+
spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
69+
70+
chained_irq_enter(chip, desc);
71+
72+
for_each_set_bit(hwirq, &pending, 32) {
73+
int irq = irq_find_mapping(hlwd->gpioc.irq.domain, hwirq);
74+
75+
generic_handle_irq(irq);
76+
}
77+
78+
chained_irq_exit(chip, desc);
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}
80+
81+
static void hlwd_gpio_irq_ack(struct irq_data *data)
82+
{
83+
struct hlwd_gpio *hlwd =
84+
gpiochip_get_data(irq_data_get_irq_chip_data(data));
85+
86+
iowrite32be(BIT(data->hwirq), hlwd->regs + HW_GPIOB_INTFLAG);
87+
}
88+
89+
static void hlwd_gpio_irq_mask(struct irq_data *data)
90+
{
91+
struct hlwd_gpio *hlwd =
92+
gpiochip_get_data(irq_data_get_irq_chip_data(data));
93+
unsigned long flags;
94+
u32 mask;
95+
96+
spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);
97+
mask = ioread32be(hlwd->regs + HW_GPIOB_INTMASK);
98+
mask &= ~BIT(data->hwirq);
99+
iowrite32be(mask, hlwd->regs + HW_GPIOB_INTMASK);
100+
spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
101+
}
102+
103+
static void hlwd_gpio_irq_unmask(struct irq_data *data)
104+
{
105+
struct hlwd_gpio *hlwd =
106+
gpiochip_get_data(irq_data_get_irq_chip_data(data));
107+
unsigned long flags;
108+
u32 mask;
109+
110+
spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);
111+
mask = ioread32be(hlwd->regs + HW_GPIOB_INTMASK);
112+
mask |= BIT(data->hwirq);
113+
iowrite32be(mask, hlwd->regs + HW_GPIOB_INTMASK);
114+
spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
115+
}
116+
117+
static void hlwd_gpio_irq_enable(struct irq_data *data)
118+
{
119+
hlwd_gpio_irq_ack(data);
120+
hlwd_gpio_irq_unmask(data);
121+
}
122+
123+
static int hlwd_gpio_irq_set_type(struct irq_data *data, unsigned int flow_type)
124+
{
125+
struct hlwd_gpio *hlwd =
126+
gpiochip_get_data(irq_data_get_irq_chip_data(data));
127+
unsigned long flags;
128+
u32 level;
129+
130+
spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);
131+
132+
switch (flow_type) {
133+
case IRQ_TYPE_LEVEL_HIGH:
134+
level = ioread32be(hlwd->regs + HW_GPIOB_INTLVL);
135+
level |= BIT(data->hwirq);
136+
iowrite32be(level, hlwd->regs + HW_GPIOB_INTLVL);
137+
break;
138+
case IRQ_TYPE_LEVEL_LOW:
139+
level = ioread32be(hlwd->regs + HW_GPIOB_INTLVL);
140+
level &= ~BIT(data->hwirq);
141+
iowrite32be(level, hlwd->regs + HW_GPIOB_INTLVL);
142+
break;
143+
default:
144+
spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
145+
return -EINVAL;
146+
}
147+
148+
spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
149+
return 0;
150+
}
151+
54152
static int hlwd_gpio_probe(struct platform_device *pdev)
55153
{
56154
struct hlwd_gpio *hlwd;
@@ -92,7 +190,43 @@ static int hlwd_gpio_probe(struct platform_device *pdev)
92190
ngpios = 32;
93191
hlwd->gpioc.ngpio = ngpios;
94192

95-
return devm_gpiochip_add_data(&pdev->dev, &hlwd->gpioc, hlwd);
193+
res = devm_gpiochip_add_data(&pdev->dev, &hlwd->gpioc, hlwd);
194+
if (res)
195+
return res;
196+
197+
/* Mask and ack all interrupts */
198+
iowrite32be(0, hlwd->regs + HW_GPIOB_INTMASK);
199+
iowrite32be(0xffffffff, hlwd->regs + HW_GPIOB_INTFLAG);
200+
201+
/*
202+
* If this GPIO controller is not marked as an interrupt controller in
203+
* the DT, return.
204+
*/
205+
if (!of_property_read_bool(pdev->dev.of_node, "interrupt-controller"))
206+
return 0;
207+
208+
hlwd->irq = platform_get_irq(pdev, 0);
209+
if (hlwd->irq < 0) {
210+
dev_info(&pdev->dev, "platform_get_irq returned %d\n",
211+
hlwd->irq);
212+
return hlwd->irq;
213+
}
214+
215+
hlwd->irqc.name = dev_name(&pdev->dev);
216+
hlwd->irqc.irq_mask = hlwd_gpio_irq_mask;
217+
hlwd->irqc.irq_unmask = hlwd_gpio_irq_unmask;
218+
hlwd->irqc.irq_enable = hlwd_gpio_irq_enable;
219+
hlwd->irqc.irq_set_type = hlwd_gpio_irq_set_type;
220+
221+
res = gpiochip_irqchip_add(&hlwd->gpioc, &hlwd->irqc, 0,
222+
handle_level_irq, IRQ_TYPE_NONE);
223+
if (res)
224+
return res;
225+
226+
gpiochip_set_chained_irqchip(&hlwd->gpioc, &hlwd->irqc,
227+
hlwd->irq, hlwd_gpio_irqhandler);
228+
229+
return 0;
96230
}
97231

98232
static const struct of_device_id hlwd_gpio_match[] = {

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