Skip to content

Commit 59879d5

Browse files
kvaneeshmpe
kvaneesh
authored and
mpe
committed
powerpc/mm/book3s64: Move book3s64 code to pgtable-book3s64
Only code movement and avoid #ifdef. Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
1 parent a42ae34 commit 59879d5

File tree

2 files changed

+54
-56
lines changed

2 files changed

+54
-56
lines changed

‎arch/powerpc/mm/pgtable-book3s64.c

Lines changed: 54 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -9,10 +9,13 @@
99

1010
#include <linux/sched.h>
1111
#include <linux/mm_types.h>
12+
#include <linux/memblock.h>
1213
#include <misc/cxl-base.h>
1314

1415
#include <asm/pgalloc.h>
1516
#include <asm/tlb.h>
17+
#include <asm/trace.h>
18+
#include <asm/powernv.h>
1619

1720
#include "mmu_decl.h"
1821
#include <trace/events/thp.h>
@@ -171,3 +174,54 @@ int __meminit remove_section_mapping(unsigned long start, unsigned long end)
171174
return hash__remove_section_mapping(start, end);
172175
}
173176
#endif /* CONFIG_MEMORY_HOTPLUG */
177+
178+
void __init mmu_partition_table_init(void)
179+
{
180+
unsigned long patb_size = 1UL << PATB_SIZE_SHIFT;
181+
unsigned long ptcr;
182+
183+
BUILD_BUG_ON_MSG((PATB_SIZE_SHIFT > 36), "Partition table size too large.");
184+
partition_tb = __va(memblock_alloc_base(patb_size, patb_size,
185+
MEMBLOCK_ALLOC_ANYWHERE));
186+
187+
/* Initialize the Partition Table with no entries */
188+
memset((void *)partition_tb, 0, patb_size);
189+
190+
/*
191+
* update partition table control register,
192+
* 64 K size.
193+
*/
194+
ptcr = __pa(partition_tb) | (PATB_SIZE_SHIFT - 12);
195+
mtspr(SPRN_PTCR, ptcr);
196+
powernv_set_nmmu_ptcr(ptcr);
197+
}
198+
199+
void mmu_partition_table_set_entry(unsigned int lpid, unsigned long dw0,
200+
unsigned long dw1)
201+
{
202+
unsigned long old = be64_to_cpu(partition_tb[lpid].patb0);
203+
204+
partition_tb[lpid].patb0 = cpu_to_be64(dw0);
205+
partition_tb[lpid].patb1 = cpu_to_be64(dw1);
206+
207+
/*
208+
* Global flush of TLBs and partition table caches for this lpid.
209+
* The type of flush (hash or radix) depends on what the previous
210+
* use of this partition ID was, not the new use.
211+
*/
212+
asm volatile("ptesync" : : : "memory");
213+
if (old & PATB_HR) {
214+
asm volatile(PPC_TLBIE_5(%0,%1,2,0,1) : :
215+
"r" (TLBIEL_INVAL_SET_LPID), "r" (lpid));
216+
asm volatile(PPC_TLBIE_5(%0,%1,2,1,1) : :
217+
"r" (TLBIEL_INVAL_SET_LPID), "r" (lpid));
218+
trace_tlbie(lpid, 0, TLBIEL_INVAL_SET_LPID, lpid, 2, 0, 1);
219+
} else {
220+
asm volatile(PPC_TLBIE_5(%0,%1,2,0,0) : :
221+
"r" (TLBIEL_INVAL_SET_LPID), "r" (lpid));
222+
trace_tlbie(lpid, 0, TLBIEL_INVAL_SET_LPID, lpid, 2, 0, 0);
223+
}
224+
/* do we need fixup here ?*/
225+
asm volatile("eieio; tlbsync; ptesync" : : : "memory");
226+
}
227+
EXPORT_SYMBOL_GPL(mmu_partition_table_set_entry);

‎arch/powerpc/mm/pgtable_64.c

Lines changed: 0 additions & 56 deletions
Original file line numberDiff line numberDiff line change
@@ -33,7 +33,6 @@
3333
#include <linux/swap.h>
3434
#include <linux/stddef.h>
3535
#include <linux/vmalloc.h>
36-
#include <linux/memblock.h>
3736
#include <linux/slab.h>
3837
#include <linux/hugetlb.h>
3938

@@ -47,13 +46,11 @@
4746
#include <asm/smp.h>
4847
#include <asm/machdep.h>
4948
#include <asm/tlb.h>
50-
#include <asm/trace.h>
5149
#include <asm/processor.h>
5250
#include <asm/cputable.h>
5351
#include <asm/sections.h>
5452
#include <asm/firmware.h>
5553
#include <asm/dma.h>
56-
#include <asm/powernv.h>
5754

5855
#include "mmu_decl.h"
5956

@@ -429,59 +426,6 @@ void pgtable_free_tlb(struct mmu_gather *tlb, void *table, int shift)
429426
}
430427
#endif
431428

432-
#ifdef CONFIG_PPC_BOOK3S_64
433-
void __init mmu_partition_table_init(void)
434-
{
435-
unsigned long patb_size = 1UL << PATB_SIZE_SHIFT;
436-
unsigned long ptcr;
437-
438-
BUILD_BUG_ON_MSG((PATB_SIZE_SHIFT > 36), "Partition table size too large.");
439-
partition_tb = __va(memblock_alloc_base(patb_size, patb_size,
440-
MEMBLOCK_ALLOC_ANYWHERE));
441-
442-
/* Initialize the Partition Table with no entries */
443-
memset((void *)partition_tb, 0, patb_size);
444-
445-
/*
446-
* update partition table control register,
447-
* 64 K size.
448-
*/
449-
ptcr = __pa(partition_tb) | (PATB_SIZE_SHIFT - 12);
450-
mtspr(SPRN_PTCR, ptcr);
451-
powernv_set_nmmu_ptcr(ptcr);
452-
}
453-
454-
void mmu_partition_table_set_entry(unsigned int lpid, unsigned long dw0,
455-
unsigned long dw1)
456-
{
457-
unsigned long old = be64_to_cpu(partition_tb[lpid].patb0);
458-
459-
partition_tb[lpid].patb0 = cpu_to_be64(dw0);
460-
partition_tb[lpid].patb1 = cpu_to_be64(dw1);
461-
462-
/*
463-
* Global flush of TLBs and partition table caches for this lpid.
464-
* The type of flush (hash or radix) depends on what the previous
465-
* use of this partition ID was, not the new use.
466-
*/
467-
asm volatile("ptesync" : : : "memory");
468-
if (old & PATB_HR) {
469-
asm volatile(PPC_TLBIE_5(%0,%1,2,0,1) : :
470-
"r" (TLBIEL_INVAL_SET_LPID), "r" (lpid));
471-
asm volatile(PPC_TLBIE_5(%0,%1,2,1,1) : :
472-
"r" (TLBIEL_INVAL_SET_LPID), "r" (lpid));
473-
trace_tlbie(lpid, 0, TLBIEL_INVAL_SET_LPID, lpid, 2, 0, 1);
474-
} else {
475-
asm volatile(PPC_TLBIE_5(%0,%1,2,0,0) : :
476-
"r" (TLBIEL_INVAL_SET_LPID), "r" (lpid));
477-
trace_tlbie(lpid, 0, TLBIEL_INVAL_SET_LPID, lpid, 2, 0, 0);
478-
}
479-
/* do we need fixup here ?*/
480-
asm volatile("eieio; tlbsync; ptesync" : : : "memory");
481-
}
482-
EXPORT_SYMBOL_GPL(mmu_partition_table_set_entry);
483-
#endif /* CONFIG_PPC_BOOK3S_64 */
484-
485429
#ifdef CONFIG_STRICT_KERNEL_RWX
486430
void mark_rodata_ro(void)
487431
{

0 commit comments

Comments
 (0)