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RDMA/hns: Init SRQ table for hip08
This patch inits hem resource for SRQ table, includes SRQWQE and SRQWQE index resource. Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
1 parent d16da11 commit 5c1f167

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9 files changed

+140
-1
lines changed

9 files changed

+140
-1
lines changed

‎drivers/infiniband/hw/hns/Makefile

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@ ccflags-y := -Idrivers/net/ethernet/hisilicon/hns3
77
obj-$(CONFIG_INFINIBAND_HNS) += hns-roce.o
88
hns-roce-objs := hns_roce_main.o hns_roce_cmd.o hns_roce_pd.o \
99
hns_roce_ah.o hns_roce_hem.o hns_roce_mr.o hns_roce_qp.o \
10-
hns_roce_cq.o hns_roce_alloc.o hns_roce_db.o
10+
hns_roce_cq.o hns_roce_alloc.o hns_roce_db.o hns_roce_srq.o
1111
obj-$(CONFIG_INFINIBAND_HNS_HIP06) += hns-roce-hw-v1.o
1212
hns-roce-hw-v1-objs := hns_roce_hw_v1.o
1313
obj-$(CONFIG_INFINIBAND_HNS_HIP08) += hns-roce-hw-v2.o

‎drivers/infiniband/hw/hns/hns_roce_alloc.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -239,6 +239,8 @@ int hns_roce_buf_alloc(struct hns_roce_dev *hr_dev, u32 size, u32 max_direct,
239239

240240
void hns_roce_cleanup_bitmap(struct hns_roce_dev *hr_dev)
241241
{
242+
if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ)
243+
hns_roce_cleanup_srq_table(hr_dev);
242244
hns_roce_cleanup_qp_table(hr_dev);
243245
hns_roce_cleanup_cq_table(hr_dev);
244246
hns_roce_cleanup_mr_table(hr_dev);

‎drivers/infiniband/hw/hns/hns_roce_device.h

Lines changed: 23 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -205,6 +205,8 @@ enum {
205205
enum hns_roce_mtt_type {
206206
MTT_TYPE_WQE,
207207
MTT_TYPE_CQE,
208+
MTT_TYPE_SRQWQE,
209+
MTT_TYPE_IDX
208210
};
209211

210212
enum {
@@ -340,6 +342,10 @@ struct hns_roce_mr_table {
340342
struct hns_roce_hem_table mtpt_table;
341343
struct hns_roce_buddy mtt_cqe_buddy;
342344
struct hns_roce_hem_table mtt_cqe_table;
345+
struct hns_roce_buddy mtt_srqwqe_buddy;
346+
struct hns_roce_hem_table mtt_srqwqe_table;
347+
struct hns_roce_buddy mtt_idx_buddy;
348+
struct hns_roce_hem_table mtt_idx_table;
343349
};
344350

345351
struct hns_roce_wq {
@@ -454,6 +460,12 @@ struct hns_roce_cq_table {
454460
struct hns_roce_hem_table table;
455461
};
456462

463+
struct hns_roce_srq_table {
464+
struct hns_roce_bitmap bitmap;
465+
struct xarray xa;
466+
struct hns_roce_hem_table table;
467+
};
468+
457469
struct hns_roce_raq_table {
458470
struct hns_roce_buf_list *e_raq_buf;
459471
};
@@ -680,6 +692,8 @@ struct hns_roce_caps {
680692
u32 max_extend_sg;
681693
int num_qps; /* 256k */
682694
int reserved_qps;
695+
u32 max_srq_sg;
696+
int num_srqs;
683697
u32 max_wqes; /* 16k */
684698
u32 max_srqs;
685699
u32 max_srq_wrs;
@@ -694,12 +708,16 @@ struct hns_roce_caps {
694708
int min_cqes;
695709
u32 min_wqes;
696710
int reserved_cqs;
711+
int reserved_srqs;
712+
u32 max_srqwqes;
697713
int num_aeq_vectors; /* 1 */
698714
int num_comp_vectors;
699715
int num_other_vectors;
700716
int num_mtpts;
701717
u32 num_mtt_segs;
702718
u32 num_cqe_segs;
719+
u32 num_srqwqe_segs;
720+
u32 num_idx_segs;
703721
int reserved_mrws;
704722
int reserved_uars;
705723
int num_pds;
@@ -713,6 +731,8 @@ struct hns_roce_caps {
713731
int irrl_entry_sz;
714732
int trrl_entry_sz;
715733
int cqc_entry_sz;
734+
int srqc_entry_sz;
735+
int idx_entry_sz;
716736
u32 pbl_ba_pg_sz;
717737
u32 pbl_buf_pg_sz;
718738
u32 pbl_hop_num;
@@ -843,6 +863,7 @@ struct hns_roce_dev {
843863
struct hns_roce_uar_table uar_table;
844864
struct hns_roce_mr_table mr_table;
845865
struct hns_roce_cq_table cq_table;
866+
struct hns_roce_srq_table srq_table;
846867
struct hns_roce_qp_table qp_table;
847868
struct hns_roce_eq_table eq_table;
848869

@@ -955,12 +976,14 @@ int hns_roce_init_mr_table(struct hns_roce_dev *hr_dev);
955976
int hns_roce_init_eq_table(struct hns_roce_dev *hr_dev);
956977
int hns_roce_init_cq_table(struct hns_roce_dev *hr_dev);
957978
int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev);
979+
int hns_roce_init_srq_table(struct hns_roce_dev *hr_dev);
958980

959981
void hns_roce_cleanup_pd_table(struct hns_roce_dev *hr_dev);
960982
void hns_roce_cleanup_mr_table(struct hns_roce_dev *hr_dev);
961983
void hns_roce_cleanup_eq_table(struct hns_roce_dev *hr_dev);
962984
void hns_roce_cleanup_cq_table(struct hns_roce_dev *hr_dev);
963985
void hns_roce_cleanup_qp_table(struct hns_roce_dev *hr_dev);
986+
void hns_roce_cleanup_srq_table(struct hns_roce_dev *hr_dev);
964987

965988
int hns_roce_bitmap_alloc(struct hns_roce_bitmap *bitmap, unsigned long *obj);
966989
void hns_roce_bitmap_free(struct hns_roce_bitmap *bitmap, unsigned long obj,

‎drivers/infiniband/hw/hns/hns_roce_hem.c

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1041,6 +1041,15 @@ void hns_roce_cleanup_hem_table(struct hns_roce_dev *hr_dev,
10411041

10421042
void hns_roce_cleanup_hem(struct hns_roce_dev *hr_dev)
10431043
{
1044+
if ((hr_dev->caps.num_idx_segs))
1045+
hns_roce_cleanup_hem_table(hr_dev,
1046+
&hr_dev->mr_table.mtt_idx_table);
1047+
if (hr_dev->caps.num_srqwqe_segs)
1048+
hns_roce_cleanup_hem_table(hr_dev,
1049+
&hr_dev->mr_table.mtt_srqwqe_table);
1050+
if (hr_dev->caps.srqc_entry_sz)
1051+
hns_roce_cleanup_hem_table(hr_dev,
1052+
&hr_dev->srq_table.table);
10441053
hns_roce_cleanup_hem_table(hr_dev, &hr_dev->cq_table.table);
10451054
if (hr_dev->caps.trrl_entry_sz)
10461055
hns_roce_cleanup_hem_table(hr_dev,

‎drivers/infiniband/hw/hns/hns_roce_hem.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -48,6 +48,8 @@ enum {
4848
/* UNMAP HEM */
4949
HEM_TYPE_MTT,
5050
HEM_TYPE_CQE,
51+
HEM_TYPE_SRQWQE,
52+
HEM_TYPE_IDX,
5153
HEM_TYPE_IRRL,
5254
HEM_TYPE_TRRL,
5355
};

‎drivers/infiniband/hw/hns/hns_roce_hw_v2.c

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1276,11 +1276,14 @@ static int hns_roce_v2_profile(struct hns_roce_dev *hr_dev)
12761276
caps->num_qps = HNS_ROCE_V2_MAX_QP_NUM;
12771277
caps->max_wqes = HNS_ROCE_V2_MAX_WQE_NUM;
12781278
caps->num_cqs = HNS_ROCE_V2_MAX_CQ_NUM;
1279+
caps->num_srqs = HNS_ROCE_V2_MAX_SRQ_NUM;
12791280
caps->max_cqes = HNS_ROCE_V2_MAX_CQE_NUM;
1281+
caps->max_srqwqes = HNS_ROCE_V2_MAX_SRQWQE_NUM;
12801282
caps->max_sq_sg = HNS_ROCE_V2_MAX_SQ_SGE_NUM;
12811283
caps->max_extend_sg = HNS_ROCE_V2_MAX_EXTEND_SGE_NUM;
12821284
caps->max_rq_sg = HNS_ROCE_V2_MAX_RQ_SGE_NUM;
12831285
caps->max_sq_inline = HNS_ROCE_V2_MAX_SQ_INLINE;
1286+
caps->max_srq_sg = HNS_ROCE_V2_MAX_SRQ_SGE_NUM;
12841287
caps->num_uars = HNS_ROCE_V2_UAR_NUM;
12851288
caps->phy_num_uars = HNS_ROCE_V2_PHY_UAR_NUM;
12861289
caps->num_aeq_vectors = HNS_ROCE_V2_AEQE_VEC_NUM;
@@ -1289,6 +1292,8 @@ static int hns_roce_v2_profile(struct hns_roce_dev *hr_dev)
12891292
caps->num_mtpts = HNS_ROCE_V2_MAX_MTPT_NUM;
12901293
caps->num_mtt_segs = HNS_ROCE_V2_MAX_MTT_SEGS;
12911294
caps->num_cqe_segs = HNS_ROCE_V2_MAX_CQE_SEGS;
1295+
caps->num_srqwqe_segs = HNS_ROCE_V2_MAX_SRQWQE_SEGS;
1296+
caps->num_idx_segs = HNS_ROCE_V2_MAX_IDX_SEGS;
12921297
caps->num_pds = HNS_ROCE_V2_MAX_PD_NUM;
12931298
caps->max_qp_init_rdma = HNS_ROCE_V2_MAX_QP_INIT_RDMA;
12941299
caps->max_qp_dest_rdma = HNS_ROCE_V2_MAX_QP_DEST_RDMA;
@@ -1299,15 +1304,18 @@ static int hns_roce_v2_profile(struct hns_roce_dev *hr_dev)
12991304
caps->irrl_entry_sz = HNS_ROCE_V2_IRRL_ENTRY_SZ;
13001305
caps->trrl_entry_sz = HNS_ROCE_V2_TRRL_ENTRY_SZ;
13011306
caps->cqc_entry_sz = HNS_ROCE_V2_CQC_ENTRY_SZ;
1307+
caps->srqc_entry_sz = HNS_ROCE_V2_SRQC_ENTRY_SZ;
13021308
caps->mtpt_entry_sz = HNS_ROCE_V2_MTPT_ENTRY_SZ;
13031309
caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ;
1310+
caps->idx_entry_sz = 4;
13041311
caps->cq_entry_sz = HNS_ROCE_V2_CQE_ENTRY_SIZE;
13051312
caps->page_size_cap = HNS_ROCE_V2_PAGE_SIZE_SUPPORTED;
13061313
caps->reserved_lkey = 0;
13071314
caps->reserved_pds = 0;
13081315
caps->reserved_mrws = 1;
13091316
caps->reserved_uars = 0;
13101317
caps->reserved_cqs = 0;
1318+
caps->reserved_srqs = 0;
13111319
caps->reserved_qps = HNS_ROCE_V2_RSV_QPS;
13121320

13131321
caps->qpc_ba_pg_sz = 0;

‎drivers/infiniband/hw/hns/hns_roce_hw_v2.h

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -50,9 +50,12 @@
5050
#define HNS_ROCE_V2_MAX_SRQ_WR 0x8000
5151
#define HNS_ROCE_V2_MAX_SRQ_SGE 0x100
5252
#define HNS_ROCE_V2_MAX_CQ_NUM 0x8000
53+
#define HNS_ROCE_V2_MAX_SRQ_NUM 0x100000
5354
#define HNS_ROCE_V2_MAX_CQE_NUM 0x10000
55+
#define HNS_ROCE_V2_MAX_SRQWQE_NUM 0x8000
5456
#define HNS_ROCE_V2_MAX_RQ_SGE_NUM 0x100
5557
#define HNS_ROCE_V2_MAX_SQ_SGE_NUM 0xff
58+
#define HNS_ROCE_V2_MAX_SRQ_SGE_NUM 0x100
5659
#define HNS_ROCE_V2_MAX_EXTEND_SGE_NUM 0x200000
5760
#define HNS_ROCE_V2_MAX_SQ_INLINE 0x20
5861
#define HNS_ROCE_V2_UAR_NUM 256
@@ -64,6 +67,8 @@
6467
#define HNS_ROCE_V2_MAX_MTPT_NUM 0x8000
6568
#define HNS_ROCE_V2_MAX_MTT_SEGS 0x1000000
6669
#define HNS_ROCE_V2_MAX_CQE_SEGS 0x1000000
70+
#define HNS_ROCE_V2_MAX_SRQWQE_SEGS 0x1000000
71+
#define HNS_ROCE_V2_MAX_IDX_SEGS 0x1000000
6772
#define HNS_ROCE_V2_MAX_PD_NUM 0x1000000
6873
#define HNS_ROCE_V2_MAX_QP_INIT_RDMA 128
6974
#define HNS_ROCE_V2_MAX_QP_DEST_RDMA 128
@@ -74,6 +79,7 @@
7479
#define HNS_ROCE_V2_IRRL_ENTRY_SZ 64
7580
#define HNS_ROCE_V2_TRRL_ENTRY_SZ 48
7681
#define HNS_ROCE_V2_CQC_ENTRY_SZ 64
82+
#define HNS_ROCE_V2_SRQC_ENTRY_SZ 64
7783
#define HNS_ROCE_V2_MTPT_ENTRY_SZ 64
7884
#define HNS_ROCE_V2_MTT_ENTRY_SZ 64
7985
#define HNS_ROCE_V2_CQE_ENTRY_SIZE 32

‎drivers/infiniband/hw/hns/hns_roce_main.c

Lines changed: 63 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -651,8 +651,58 @@ static int hns_roce_init_hem(struct hns_roce_dev *hr_dev)
651651
goto err_unmap_trrl;
652652
}
653653

654+
if (hr_dev->caps.srqc_entry_sz) {
655+
ret = hns_roce_init_hem_table(hr_dev, &hr_dev->srq_table.table,
656+
HEM_TYPE_SRQC,
657+
hr_dev->caps.srqc_entry_sz,
658+
hr_dev->caps.num_srqs, 1);
659+
if (ret) {
660+
dev_err(dev,
661+
"Failed to init SRQ context memory, aborting.\n");
662+
goto err_unmap_cq;
663+
}
664+
}
665+
666+
if (hr_dev->caps.num_srqwqe_segs) {
667+
ret = hns_roce_init_hem_table(hr_dev,
668+
&hr_dev->mr_table.mtt_srqwqe_table,
669+
HEM_TYPE_SRQWQE,
670+
hr_dev->caps.mtt_entry_sz,
671+
hr_dev->caps.num_srqwqe_segs, 1);
672+
if (ret) {
673+
dev_err(dev,
674+
"Failed to init MTT srqwqe memory, aborting.\n");
675+
goto err_unmap_srq;
676+
}
677+
}
678+
679+
if (hr_dev->caps.num_idx_segs) {
680+
ret = hns_roce_init_hem_table(hr_dev,
681+
&hr_dev->mr_table.mtt_idx_table,
682+
HEM_TYPE_IDX,
683+
hr_dev->caps.idx_entry_sz,
684+
hr_dev->caps.num_idx_segs, 1);
685+
if (ret) {
686+
dev_err(dev,
687+
"Failed to init MTT idx memory, aborting.\n");
688+
goto err_unmap_srqwqe;
689+
}
690+
}
691+
654692
return 0;
655693

694+
err_unmap_srqwqe:
695+
if (hr_dev->caps.num_srqwqe_segs)
696+
hns_roce_cleanup_hem_table(hr_dev,
697+
&hr_dev->mr_table.mtt_srqwqe_table);
698+
699+
err_unmap_srq:
700+
if (hr_dev->caps.srqc_entry_sz)
701+
hns_roce_cleanup_hem_table(hr_dev, &hr_dev->srq_table.table);
702+
703+
err_unmap_cq:
704+
hns_roce_cleanup_hem_table(hr_dev, &hr_dev->cq_table.table);
705+
656706
err_unmap_trrl:
657707
if (hr_dev->caps.trrl_entry_sz)
658708
hns_roce_cleanup_hem_table(hr_dev,
@@ -732,8 +782,21 @@ static int hns_roce_setup_hca(struct hns_roce_dev *hr_dev)
732782
goto err_cq_table_free;
733783
}
734784

785+
if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) {
786+
ret = hns_roce_init_srq_table(hr_dev);
787+
if (ret) {
788+
dev_err(dev,
789+
"Failed to init share receive queue table.\n");
790+
goto err_qp_table_free;
791+
}
792+
}
793+
735794
return 0;
736795

796+
err_qp_table_free:
797+
if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ)
798+
hns_roce_cleanup_qp_table(hr_dev);
799+
737800
err_cq_table_free:
738801
hns_roce_cleanup_cq_table(hr_dev);
739802

‎drivers/infiniband/hw/hns/hns_roce_srq.c

Lines changed: 26 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,26 @@
1+
// SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
2+
/*
3+
* Copyright (c) 2018 Hisilicon Limited.
4+
*/
5+
6+
#include <rdma/ib_umem.h>
7+
#include <rdma/hns-abi.h>
8+
#include "hns_roce_device.h"
9+
#include "hns_roce_cmd.h"
10+
#include "hns_roce_hem.h"
11+
12+
int hns_roce_init_srq_table(struct hns_roce_dev *hr_dev)
13+
{
14+
struct hns_roce_srq_table *srq_table = &hr_dev->srq_table;
15+
16+
xa_init(&srq_table->xa);
17+
18+
return hns_roce_bitmap_init(&srq_table->bitmap, hr_dev->caps.num_srqs,
19+
hr_dev->caps.num_srqs - 1,
20+
hr_dev->caps.reserved_srqs, 0);
21+
}
22+
23+
void hns_roce_cleanup_srq_table(struct hns_roce_dev *hr_dev)
24+
{
25+
hns_roce_bitmap_cleanup(&hr_dev->srq_table.bitmap);
26+
}

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