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Nobuhiro Iwamatsudavem330
Nobuhiro Iwamatsu
authored and
davem330
committed
net/sh-eth: Check return value of sh_eth_reset when chip reset fail
The sh_eth_reset function resets chip, but this performs nothing when failed. This changes sh_eth_reset return an error, when this failed in reset. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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‎drivers/net/ethernet/renesas/sh_eth.c

Lines changed: 56 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -130,6 +130,8 @@ static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
130130
#elif defined(CONFIG_CPU_SUBTYPE_SH7757)
131131
#define SH_ETH_HAS_BOTH_MODULES 1
132132
#define SH_ETH_HAS_TSU 1
133+
static int sh_eth_check_reset(struct net_device *ndev);
134+
133135
static void sh_eth_set_duplex(struct net_device *ndev)
134136
{
135137
struct sh_eth_private *mdp = netdev_priv(ndev);
@@ -204,23 +206,19 @@ static void sh_eth_chip_reset_giga(struct net_device *ndev)
204206
}
205207

206208
static int sh_eth_is_gether(struct sh_eth_private *mdp);
207-
static void sh_eth_reset(struct net_device *ndev)
209+
static int sh_eth_reset(struct net_device *ndev)
208210
{
209211
struct sh_eth_private *mdp = netdev_priv(ndev);
210-
int cnt = 100;
212+
int ret = 0;
211213

212214
if (sh_eth_is_gether(mdp)) {
213215
sh_eth_write(ndev, 0x03, EDSR);
214216
sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
215217
EDMR);
216-
while (cnt > 0) {
217-
if (!(sh_eth_read(ndev, EDMR) & 0x3))
218-
break;
219-
mdelay(1);
220-
cnt--;
221-
}
222-
if (cnt < 0)
223-
printk(KERN_ERR "Device reset fail\n");
218+
219+
ret = sh_eth_check_reset(ndev);
220+
if (ret)
221+
goto out;
224222

225223
/* Table Init */
226224
sh_eth_write(ndev, 0x0, TDLAR);
@@ -238,6 +236,9 @@ static void sh_eth_reset(struct net_device *ndev)
238236
sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
239237
EDMR);
240238
}
239+
240+
out:
241+
return ret;
241242
}
242243

243244
static void sh_eth_set_duplex_giga(struct net_device *ndev)
@@ -310,6 +311,7 @@ static struct sh_eth_cpu_data *sh_eth_get_cpu_data(struct sh_eth_private *mdp)
310311

311312
#elif defined(CONFIG_CPU_SUBTYPE_SH7734) || defined(CONFIG_CPU_SUBTYPE_SH7763)
312313
#define SH_ETH_HAS_TSU 1
314+
static int sh_eth_check_reset(struct net_device *ndev);
313315
static void sh_eth_reset_hw_crc(struct net_device *ndev);
314316

315317
static void sh_eth_chip_reset(struct net_device *ndev)
@@ -381,20 +383,16 @@ static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
381383
#endif
382384
};
383385

384-
static void sh_eth_reset(struct net_device *ndev)
386+
static int sh_eth_reset(struct net_device *ndev)
385387
{
386-
int cnt = 100;
388+
int ret = 0;
387389

388390
sh_eth_write(ndev, EDSR_ENALL, EDSR);
389391
sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER, EDMR);
390-
while (cnt > 0) {
391-
if (!(sh_eth_read(ndev, EDMR) & 0x3))
392-
break;
393-
mdelay(1);
394-
cnt--;
395-
}
396-
if (cnt == 0)
397-
printk(KERN_ERR "Device reset fail\n");
392+
393+
ret = sh_eth_check_reset(ndev);
394+
if (ret)
395+
goto out;
398396

399397
/* Table Init */
400398
sh_eth_write(ndev, 0x0, TDLAR);
@@ -412,6 +410,8 @@ static void sh_eth_reset(struct net_device *ndev)
412410
/* Select MII mode */
413411
if (sh_eth_my_cpu_data.select_mii)
414412
sh_eth_select_mii(ndev);
413+
out:
414+
return ret;
415415
}
416416

417417
static void sh_eth_reset_hw_crc(struct net_device *ndev)
@@ -422,6 +422,8 @@ static void sh_eth_reset_hw_crc(struct net_device *ndev)
422422

423423
#elif defined(CONFIG_ARCH_R8A7740)
424424
#define SH_ETH_HAS_TSU 1
425+
static int sh_eth_check_reset(struct net_device *ndev);
426+
425427
static void sh_eth_chip_reset(struct net_device *ndev)
426428
{
427429
struct sh_eth_private *mdp = netdev_priv(ndev);
@@ -433,20 +435,16 @@ static void sh_eth_chip_reset(struct net_device *ndev)
433435
sh_eth_select_mii(ndev);
434436
}
435437

436-
static void sh_eth_reset(struct net_device *ndev)
438+
static int sh_eth_reset(struct net_device *ndev)
437439
{
438-
int cnt = 100;
440+
int ret = 0;
439441

440442
sh_eth_write(ndev, EDSR_ENALL, EDSR);
441443
sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER, EDMR);
442-
while (cnt > 0) {
443-
if (!(sh_eth_read(ndev, EDMR) & 0x3))
444-
break;
445-
mdelay(1);
446-
cnt--;
447-
}
448-
if (cnt == 0)
449-
printk(KERN_ERR "Device reset fail\n");
444+
445+
ret = sh_eth_check_reset(ndev);
446+
if (ret)
447+
goto out;
450448

451449
/* Table Init */
452450
sh_eth_write(ndev, 0x0, TDLAR);
@@ -457,6 +455,9 @@ static void sh_eth_reset(struct net_device *ndev)
457455
sh_eth_write(ndev, 0x0, RDFAR);
458456
sh_eth_write(ndev, 0x0, RDFXR);
459457
sh_eth_write(ndev, 0x0, RDFFR);
458+
459+
out:
460+
return ret;
460461
}
461462

462463
static void sh_eth_set_duplex(struct net_device *ndev)
@@ -565,11 +566,31 @@ static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
565566

566567
#if defined(SH_ETH_RESET_DEFAULT)
567568
/* Chip Reset */
568-
static void sh_eth_reset(struct net_device *ndev)
569+
static int sh_eth_reset(struct net_device *ndev)
569570
{
570571
sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER, EDMR);
571572
mdelay(3);
572573
sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER, EDMR);
574+
575+
return 0;
576+
}
577+
#else
578+
static int sh_eth_check_reset(struct net_device *ndev)
579+
{
580+
int ret = 0;
581+
int cnt = 100;
582+
583+
while (cnt > 0) {
584+
if (!(sh_eth_read(ndev, EDMR) & 0x3))
585+
break;
586+
mdelay(1);
587+
cnt--;
588+
}
589+
if (cnt < 0) {
590+
printk(KERN_ERR "Device reset fail\n");
591+
ret = -ETIMEDOUT;
592+
}
593+
return ret;
573594
}
574595
#endif
575596

@@ -924,7 +945,9 @@ static int sh_eth_dev_init(struct net_device *ndev)
924945
u32 val;
925946

926947
/* Soft Reset */
927-
sh_eth_reset(ndev);
948+
ret = sh_eth_reset(ndev);
949+
if (ret)
950+
goto out;
928951

929952
/* Descriptor format */
930953
sh_eth_ring_format(ndev);
@@ -998,6 +1021,7 @@ static int sh_eth_dev_init(struct net_device *ndev)
9981021

9991022
netif_start_queue(ndev);
10001023

1024+
out:
10011025
return ret;
10021026
}
10031027

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