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aikmpe
aik
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powerpc/iommu_api: Move IOMMU groups setup to a single place
Registering new IOMMU groups and adding devices to them are separated in code and the latter is dug in the DMA setup code which it does not really belong to. This moved IOMMU groups setup to a separate helper which registers a group and adds devices as before. This does not make a difference as IOMMU groups are not used anyway; the only dependency here is that iommu_add_device() requires a valid pointer to an iommu_table (set by set_iommu_table_base()). To keep the old behaviour, this does not add new IOMMU groups for PEs with no DMA weight and also skips NVLink bridges which do not have pci_controller_ops::setup_bridge (the normal way of adding PEs). Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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‎arch/powerpc/platforms/powernv/pci-ioda.c

Lines changed: 68 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -1533,6 +1533,9 @@ void pnv_pci_sriov_disable(struct pci_dev *pdev)
15331533

15341534
static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
15351535
struct pnv_ioda_pe *pe);
1536+
#ifdef CONFIG_IOMMU_API
1537+
static void pnv_ioda_setup_bus_iommu_group(struct pnv_ioda_pe *pe);
1538+
#endif
15361539
static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs)
15371540
{
15381541
struct pci_bus *bus;
@@ -1586,6 +1589,9 @@ static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs)
15861589
mutex_unlock(&phb->ioda.pe_list_mutex);
15871590

15881591
pnv_pci_ioda2_setup_dma_pe(phb, pe);
1592+
#ifdef CONFIG_IOMMU_API
1593+
pnv_ioda_setup_bus_iommu_group(pe);
1594+
#endif
15891595
}
15901596
}
15911597

@@ -1925,21 +1931,16 @@ static u64 pnv_pci_ioda_dma_get_required_mask(struct pci_dev *pdev)
19251931
return mask;
19261932
}
19271933

1928-
static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe,
1929-
struct pci_bus *bus,
1930-
bool add_to_group)
1934+
static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, struct pci_bus *bus)
19311935
{
19321936
struct pci_dev *dev;
19331937

19341938
list_for_each_entry(dev, &bus->devices, bus_list) {
19351939
set_iommu_table_base(&dev->dev, pe->table_group.tables[0]);
19361940
set_dma_offset(&dev->dev, pe->tce_bypass_base);
1937-
if (add_to_group)
1938-
iommu_add_device(&pe->table_group, &dev->dev);
19391941

19401942
if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1941-
pnv_ioda_setup_bus_dma(pe, dev->subordinate,
1942-
add_to_group);
1943+
pnv_ioda_setup_bus_dma(pe, dev->subordinate);
19431944
}
19441945
}
19451946

@@ -2369,7 +2370,7 @@ static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb,
23692370
iommu_init_table(tbl, phb->hose->node);
23702371

23712372
if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
2372-
pnv_ioda_setup_bus_dma(pe, pe->pbus, true);
2373+
pnv_ioda_setup_bus_dma(pe, pe->pbus);
23732374

23742375
return;
23752376
fail:
@@ -2602,7 +2603,7 @@ static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group)
26022603
pnv_pci_ioda2_set_bypass(pe, false);
26032604
pnv_pci_ioda2_unset_window(&pe->table_group, 0);
26042605
if (pe->pbus)
2605-
pnv_ioda_setup_bus_dma(pe, pe->pbus, false);
2606+
pnv_ioda_setup_bus_dma(pe, pe->pbus);
26062607
iommu_tce_table_put(tbl);
26072608
}
26082609

@@ -2613,7 +2614,7 @@ static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group)
26132614

26142615
pnv_pci_ioda2_setup_default_config(pe);
26152616
if (pe->pbus)
2616-
pnv_ioda_setup_bus_dma(pe, pe->pbus, false);
2617+
pnv_ioda_setup_bus_dma(pe, pe->pbus);
26172618
}
26182619

26192620
static struct iommu_table_group_ops pnv_pci_ioda2_ops = {
@@ -2730,12 +2731,68 @@ static struct iommu_table_group_ops pnv_pci_ioda2_npu_ops = {
27302731
.release_ownership = pnv_ioda2_release_ownership,
27312732
};
27322733

2734+
static void pnv_ioda_setup_bus_iommu_group_add_devices(struct pnv_ioda_pe *pe,
2735+
struct pci_bus *bus)
2736+
{
2737+
struct pci_dev *dev;
2738+
2739+
list_for_each_entry(dev, &bus->devices, bus_list) {
2740+
iommu_add_device(&pe->table_group, &dev->dev);
2741+
2742+
if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
2743+
pnv_ioda_setup_bus_iommu_group_add_devices(pe,
2744+
dev->subordinate);
2745+
}
2746+
}
2747+
2748+
static void pnv_ioda_setup_bus_iommu_group(struct pnv_ioda_pe *pe)
2749+
{
2750+
if (!pnv_pci_ioda_pe_dma_weight(pe))
2751+
return;
2752+
2753+
iommu_register_group(&pe->table_group, pe->phb->hose->global_number,
2754+
pe->pe_number);
2755+
2756+
/*
2757+
* set_iommu_table_base(&pe->pdev->dev, tbl) should have been called
2758+
* by now
2759+
*/
2760+
if (pe->flags & PNV_IODA_PE_DEV)
2761+
iommu_add_device(&pe->table_group, &pe->pdev->dev);
2762+
else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
2763+
pnv_ioda_setup_bus_iommu_group_add_devices(pe, pe->pbus);
2764+
}
2765+
27332766
static void pnv_pci_ioda_setup_iommu_api(void)
27342767
{
27352768
struct pci_controller *hose, *tmp;
27362769
struct pnv_phb *phb;
27372770
struct pnv_ioda_pe *pe, *gpe;
27382771

2772+
/*
2773+
* There are 4 types of PEs:
2774+
* - PNV_IODA_PE_BUS: a downstream port with an adapter,
2775+
* created from pnv_pci_setup_bridge();
2776+
* - PNV_IODA_PE_BUS_ALL: a PCI-PCIX bridge with devices behind it,
2777+
* created from pnv_pci_setup_bridge();
2778+
* - PNV_IODA_PE_VF: a SRIOV virtual function,
2779+
* created from pnv_pcibios_sriov_enable();
2780+
* - PNV_IODA_PE_DEV: an NPU or OCAPI device,
2781+
* created from pnv_pci_ioda_fixup().
2782+
*
2783+
* Normally a PE is represented by an IOMMU group, however for
2784+
* devices with side channels the groups need to be more strict.
2785+
*/
2786+
list_for_each_entry(hose, &hose_list, list_node) {
2787+
phb = hose->private_data;
2788+
2789+
if (phb->type == PNV_PHB_NPU_NVLINK)
2790+
continue;
2791+
2792+
list_for_each_entry(pe, &phb->ioda.pe_list, list)
2793+
pnv_ioda_setup_bus_iommu_group(pe);
2794+
}
2795+
27392796
/*
27402797
* Now we have all PHBs discovered, time to add NPU devices to
27412798
* the corresponding IOMMU groups.
@@ -2796,9 +2853,6 @@ static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
27962853
/* TVE #1 is selected by PCI address bit 59 */
27972854
pe->tce_bypass_base = 1ull << 59;
27982855

2799-
iommu_register_group(&pe->table_group, phb->hose->global_number,
2800-
pe->pe_number);
2801-
28022856
/* The PE will reserve all possible 32-bits space */
28032857
pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n",
28042858
phb->ioda.m32_pci_base);
@@ -2819,7 +2873,7 @@ static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
28192873
return;
28202874

28212875
if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
2822-
pnv_ioda_setup_bus_dma(pe, pe->pbus, true);
2876+
pnv_ioda_setup_bus_dma(pe, pe->pbus);
28232877
}
28242878

28252879
int64_t pnv_opal_pci_msi_eoi(struct irq_chip *chip, unsigned int hw_irq)

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