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Alexander DuyckJeff Kirsher
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ixgbevf: Use igb style interrupt masks instead of ixgbe style
The interrupt registers accessed in ixgbevf are more similar to the igb style registers than they are to the ixgbe style registers. As such we would be better off setting up the code for the EICS, EIMS, EICS, EIAM, and EIAC like we do in igb instead of ixgbe. Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Signed-off-by: Greg Rose <gregory.v.rose@intel.com> Tested-by: Sibai Li <sibai.li@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
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-146
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3 files changed

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-146
lines changed

drivers/net/ethernet/intel/ixgbevf/defines.h

Lines changed: 2 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -264,32 +264,9 @@ struct ixgbe_adv_tx_context_desc {
264264

265265
/* Interrupt register bitmasks */
266266

267-
/* Extended Interrupt Cause Read */
268-
#define IXGBE_EICR_RTX_QUEUE 0x0000FFFF /* RTx Queue Interrupt */
269-
#define IXGBE_EICR_MAILBOX 0x00080000 /* VF to PF Mailbox Interrupt */
270-
#define IXGBE_EICR_OTHER 0x80000000 /* Interrupt Cause Active */
271-
272-
/* Extended Interrupt Cause Set */
273-
#define IXGBE_EICS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
274-
#define IXGBE_EICS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */
275-
#define IXGBE_EICS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
276-
277-
/* Extended Interrupt Mask Set */
278-
#define IXGBE_EIMS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
279-
#define IXGBE_EIMS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */
280-
#define IXGBE_EIMS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
281-
282-
/* Extended Interrupt Mask Clear */
283-
#define IXGBE_EIMC_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
284-
#define IXGBE_EIMC_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */
285-
#define IXGBE_EIMC_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
286-
287-
#define IXGBE_EIMS_ENABLE_MASK ( \
288-
IXGBE_EIMS_RTX_QUEUE | \
289-
IXGBE_EIMS_MAILBOX | \
290-
IXGBE_EIMS_OTHER)
291-
292267
#define IXGBE_EITR_CNT_WDIS 0x80000000
268+
#define IXGBE_MAX_EITR 0x00000FF8
269+
#define IXGBE_MIN_EITR 8
293270

294271
/* Error Codes */
295272
#define IXGBE_ERR_INVALID_MAC_ADDR -1

drivers/net/ethernet/intel/ixgbevf/ixgbevf.h

Lines changed: 23 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -118,6 +118,8 @@ struct ixgbevf_ring {
118118

119119
struct ixgbevf_ring_container {
120120
struct ixgbevf_ring *ring; /* pointer to linked list of rings */
121+
unsigned int total_bytes; /* total bytes processed this int */
122+
unsigned int total_packets; /* total packets processed this int */
121123
u8 count; /* total number of rings in vector */
122124
u8 itr; /* current ITR setting for ring */
123125
};
@@ -131,13 +133,25 @@ struct ixgbevf_ring_container {
131133
*/
132134
struct ixgbevf_q_vector {
133135
struct ixgbevf_adapter *adapter;
136+
u16 v_idx; /* index of q_vector within array, also used for
137+
* finding the bit in EICR and friends that
138+
* represents the vector for this ring */
139+
u16 itr; /* Interrupt throttle rate written to EITR */
134140
struct napi_struct napi;
135141
struct ixgbevf_ring_container rx, tx;
136-
u32 eitr;
137-
int v_idx; /* vector index in list */
138142
char name[IFNAMSIZ + 9];
139143
};
140144

145+
/*
146+
* microsecond values for various ITR rates shifted by 2 to fit itr register
147+
* with the first 3 bits reserved 0
148+
*/
149+
#define IXGBE_MIN_RSC_ITR 24
150+
#define IXGBE_100K_ITR 40
151+
#define IXGBE_20K_ITR 200
152+
#define IXGBE_10K_ITR 400
153+
#define IXGBE_8K_ITR 500
154+
141155
/* Helper macros to switch between ints/sec and what the register uses.
142156
* And yes, it's the same math going both ways. The lowest value
143157
* supported by all of the ixgbe hardware is 8.
@@ -176,12 +190,16 @@ struct ixgbevf_adapter {
176190
struct ixgbevf_q_vector *q_vector[MAX_MSIX_Q_VECTORS];
177191

178192
/* Interrupt Throttle Rate */
179-
u32 itr_setting;
193+
u16 rx_itr_setting;
194+
u16 tx_itr_setting;
195+
196+
/* interrupt masks */
197+
u32 eims_enable_mask;
198+
u32 eims_other;
180199

181200
/* TX */
182201
struct ixgbevf_ring *tx_ring; /* One per active queue */
183202
int num_tx_queues;
184-
u16 tx_itr_setting;
185203
u64 restart_queue;
186204
u64 hw_csum_tx_good;
187205
u64 lsc_int;
@@ -192,7 +210,6 @@ struct ixgbevf_adapter {
192210
/* RX */
193211
struct ixgbevf_ring *rx_ring; /* One per active queue */
194212
int num_rx_queues;
195-
u16 rx_itr_setting;
196213
u64 hw_csum_rx_error;
197214
u64 hw_rx_no_dma_resources;
198215
u64 hw_csum_rx_good;
@@ -265,7 +282,7 @@ extern void ixgbevf_free_rx_resources(struct ixgbevf_adapter *,
265282
extern void ixgbevf_free_tx_resources(struct ixgbevf_adapter *,
266283
struct ixgbevf_ring *);
267284
extern void ixgbevf_update_stats(struct ixgbevf_adapter *adapter);
268-
285+
void ixgbevf_write_eitr(struct ixgbevf_q_vector *);
269286
extern int ethtool_ioctl(struct ifreq *ifr);
270287

271288
extern void ixgbe_napi_add_all(struct ixgbevf_adapter *adapter);

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