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Jeffrey Hugobebarino
Jeffrey Hugo
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bebarino
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clk: qcom: smd: Add support for MSM8998 rpm clocks
Add rpm smd clocks, PMIC and bus clocks which are required on MSM8998 for clients to vote on. Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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‎Documentation/devicetree/bindings/clock/qcom,rpmcc.txt

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@@ -16,6 +16,7 @@ Required properties :
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"qcom,rpmcc-msm8974", "qcom,rpmcc"
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"qcom,rpmcc-apq8064", "qcom,rpmcc"
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"qcom,rpmcc-msm8996", "qcom,rpmcc"
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"qcom,rpmcc-msm8998", "qcom,rpmcc"
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"qcom,rpmcc-qcs404", "qcom,rpmcc"
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- #clock-cells : shall contain 1

‎drivers/clk/qcom/clk-smd-rpm.c

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@@ -655,10 +655,73 @@ static const struct rpm_smd_clk_desc rpm_clk_qcs404 = {
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.num_clks = ARRAY_SIZE(qcs404_clks),
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};
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/* msm8998 */
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DEFINE_CLK_SMD_RPM(msm8998, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
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DEFINE_CLK_SMD_RPM(msm8998, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2);
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DEFINE_CLK_SMD_RPM(msm8998, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0);
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DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, div_clk1, div_clk1_a, 0xb);
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DEFINE_CLK_SMD_RPM(msm8998, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0);
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DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, ln_bb_clk1, ln_bb_clk1_a, 1);
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DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, ln_bb_clk2, ln_bb_clk2_a, 2);
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DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, ln_bb_clk3_pin, ln_bb_clk3_a_pin,
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3);
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DEFINE_CLK_SMD_RPM(msm8998, mmssnoc_axi_rpm_clk, mmssnoc_axi_rpm_a_clk,
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QCOM_SMD_RPM_MMAXI_CLK, 0);
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DEFINE_CLK_SMD_RPM(msm8998, aggre1_noc_clk, aggre1_noc_a_clk,
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QCOM_SMD_RPM_AGGR_CLK, 1);
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DEFINE_CLK_SMD_RPM(msm8998, aggre2_noc_clk, aggre2_noc_a_clk,
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QCOM_SMD_RPM_AGGR_CLK, 2);
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DEFINE_CLK_SMD_RPM_QDSS(msm8998, qdss_clk, qdss_a_clk,
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QCOM_SMD_RPM_MISC_CLK, 1);
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DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, rf_clk1, rf_clk1_a, 4);
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DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, rf_clk2_pin, rf_clk2_a_pin, 5);
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DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, rf_clk3, rf_clk3_a, 6);
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DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, rf_clk3_pin, rf_clk3_a_pin, 6);
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static struct clk_smd_rpm *msm8998_clks[] = {
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[RPM_SMD_SNOC_CLK] = &msm8998_snoc_clk,
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[RPM_SMD_SNOC_A_CLK] = &msm8998_snoc_a_clk,
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[RPM_SMD_CNOC_CLK] = &msm8998_cnoc_clk,
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[RPM_SMD_CNOC_A_CLK] = &msm8998_cnoc_a_clk,
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[RPM_SMD_CE1_CLK] = &msm8998_ce1_clk,
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[RPM_SMD_CE1_A_CLK] = &msm8998_ce1_a_clk,
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[RPM_SMD_DIV_CLK1] = &msm8998_div_clk1,
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[RPM_SMD_DIV_A_CLK1] = &msm8998_div_clk1_a,
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[RPM_SMD_IPA_CLK] = &msm8998_ipa_clk,
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[RPM_SMD_IPA_A_CLK] = &msm8998_ipa_a_clk,
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[RPM_SMD_LN_BB_CLK1] = &msm8998_ln_bb_clk1,
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[RPM_SMD_LN_BB_CLK1_A] = &msm8998_ln_bb_clk1_a,
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[RPM_SMD_LN_BB_CLK2] = &msm8998_ln_bb_clk2,
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[RPM_SMD_LN_BB_CLK2_A] = &msm8998_ln_bb_clk2_a,
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[RPM_SMD_LN_BB_CLK3_PIN] = &msm8998_ln_bb_clk3_pin,
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[RPM_SMD_LN_BB_CLK3_A_PIN] = &msm8998_ln_bb_clk3_a_pin,
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[RPM_SMD_MMAXI_CLK] = &msm8998_mmssnoc_axi_rpm_clk,
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[RPM_SMD_MMAXI_A_CLK] = &msm8998_mmssnoc_axi_rpm_a_clk,
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[RPM_SMD_AGGR1_NOC_CLK] = &msm8998_aggre1_noc_clk,
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[RPM_SMD_AGGR1_NOC_A_CLK] = &msm8998_aggre1_noc_a_clk,
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[RPM_SMD_AGGR2_NOC_CLK] = &msm8998_aggre2_noc_clk,
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[RPM_SMD_AGGR2_NOC_A_CLK] = &msm8998_aggre2_noc_a_clk,
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[RPM_SMD_QDSS_CLK] = &msm8998_qdss_clk,
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[RPM_SMD_QDSS_A_CLK] = &msm8998_qdss_a_clk,
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[RPM_SMD_RF_CLK1] = &msm8998_rf_clk1,
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[RPM_SMD_RF_CLK1_A] = &msm8998_rf_clk1_a,
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[RPM_SMD_RF_CLK2_PIN] = &msm8998_rf_clk2_pin,
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[RPM_SMD_RF_CLK2_A_PIN] = &msm8998_rf_clk2_a_pin,
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[RPM_SMD_RF_CLK3] = &msm8998_rf_clk3,
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[RPM_SMD_RF_CLK3_A] = &msm8998_rf_clk3_a,
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[RPM_SMD_RF_CLK3_PIN] = &msm8998_rf_clk3_pin,
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[RPM_SMD_RF_CLK3_A_PIN] = &msm8998_rf_clk3_a_pin,
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};
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static const struct rpm_smd_clk_desc rpm_clk_msm8998 = {
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.clks = msm8998_clks,
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.num_clks = ARRAY_SIZE(msm8998_clks),
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};
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static const struct of_device_id rpm_smd_clk_match_table[] = {
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{ .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916 },
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{ .compatible = "qcom,rpmcc-msm8974", .data = &rpm_clk_msm8974 },
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{ .compatible = "qcom,rpmcc-msm8996", .data = &rpm_clk_msm8996 },
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{ .compatible = "qcom,rpmcc-msm8998", .data = &rpm_clk_msm8998 },
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{ .compatible = "qcom,rpmcc-qcs404", .data = &rpm_clk_qcs404 },
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{ }
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};

‎include/dt-bindings/clock/qcom,rpmcc.h

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@@ -127,5 +127,15 @@
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#define RPM_SMD_BIMC_GPU_A_CLK 77
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#define RPM_SMD_QPIC_CLK 78
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#define RPM_SMD_QPIC_CLK_A 79
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#define RPM_SMD_LN_BB_CLK1 80
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#define RPM_SMD_LN_BB_CLK1_A 81
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#define RPM_SMD_LN_BB_CLK2 82
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#define RPM_SMD_LN_BB_CLK2_A 83
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#define RPM_SMD_LN_BB_CLK3_PIN 84
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#define RPM_SMD_LN_BB_CLK3_A_PIN 85
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#define RPM_SMD_RF_CLK3 86
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#define RPM_SMD_RF_CLK3_A 87
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#define RPM_SMD_RF_CLK3_PIN 88
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#define RPM_SMD_RF_CLK3_A_PIN 89
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#endif

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