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miquelraynalMarc Zyngier
miquelraynal
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Marc Zyngier
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irqchip/irq-mvebu-sei: Add new driver for Marvell SEI
This is a cascaded interrupt controller in the AP806 GIC that collapses SEIs (System Error Interrupt) coming from the AP and the CPs (through the ICU). The SEI handles up to 64 interrupts. The first 21 interrupts are wired from the AP. The next 43 interrupts are from the CPs and are triggered through MSI messages. To handle this complexity, the driver has to declare to the upper layer: one IRQ domain for the wired interrupts, one IRQ domain for the MSIs; and acts as a MSI controller ('parent') by declaring an MSI domain. Suggested-by: Haim Boot <hayim@marvell.com> Suggested-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
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‎drivers/irqchip/Kconfig

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@@ -310,6 +310,9 @@ config MVEBU_ODMI
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config MVEBU_PIC
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bool
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config MVEBU_SEI
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bool
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config LS_SCFG_MSI
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def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
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depends on PCI && PCI_MSI

‎drivers/irqchip/Makefile

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@@ -76,6 +76,7 @@ obj-$(CONFIG_MVEBU_GICP) += irq-mvebu-gicp.o
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obj-$(CONFIG_MVEBU_ICU) += irq-mvebu-icu.o
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obj-$(CONFIG_MVEBU_ODMI) += irq-mvebu-odmi.o
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obj-$(CONFIG_MVEBU_PIC) += irq-mvebu-pic.o
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obj-$(CONFIG_MVEBU_SEI) += irq-mvebu-sei.o
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obj-$(CONFIG_LS_SCFG_MSI) += irq-ls-scfg-msi.o
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obj-$(CONFIG_EZNPS_GIC) += irq-eznps.o
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obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o irq-aspeed-i2c-ic.o

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